Interesting problem – Latches in series

Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?

Figure 1 : 100 negative level-sensitive latches in series

As we know, setup check between latches of same polarity (both positive or negative) is zero cycle with half cycle of time borrow allowed as shown in figure 2 below for negative level-sensitive latches:

Figure 2: Setup check between two negative level-sensitive latches

So, if there are a number of same polarity latches, all will form zero cycle setup check with the next latch; resulting in overall zero cycle phase shift.

As is shown in figure 3, all the latches in series are borrowing time, but allowing any actual phase shift to happen. If we have a design with all latches, there cannot be a next state calculation if all the latches are either positive level-sensitive or negative level-sensitive. In other words, for state-machine implementation, there should not be latches of same polarity in series.

Figure 3 : Timing for 100 latches in series

Hope you’ve found this post useful. Let us know what you think in the comments.

Also read:

• Build a latch using a 2:1 multiplexer
• Multicycle paths handling in STA
• Latchup in CMOS devices
• Lockup latch - principle, application and timing
• Data checks - all about data setup and data hold checks

STA

Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circuit without actually simulating it. In this post, we have tried to list down all the posts that an STA engineer cannot do without. Please add your feedback in comments to make reading it a more meaningful experience.

• Setup and hold interview questions

• Clock gating concepts
• Setup time and hold time - static timing analysis - Definition and detailed discussion on setup time and hold time, setup hold violations and how to fix them

• Metastability - This post discusses the basics of metastability and how to avoid it.

• Problem: clock gating checks at a complex gate - An exercise to analyze the requirements of clock gating checks at a complex gate

• Lockup latch - The basics of lockup latch, both from timing and DFT perspective have been discussed in this post.

• Lockup latches vs. lockup registers - Provides an insight into the situations where lockup latches and lockup registers can be useful.

• Clock latency - Read this if you wish to get acquainted with the terminology related to clock latency

• Data checks - Non-sequential setup and hold checks have been discussed, very useful for beginners

• Modeling skew requirements with the help of data checks - Explains with an example how data checks can be used to maintain skew requirements

• What is static timing analysis - Defines static timing analysis and its scope

• Setup checks and hold checks for reg-to-reg paths - Discusses the default setup and hold checks for timing paths starting from and ending at registers

• Setup checks and hold checks for register-to-latch paths - Discusses the default setup and hold checks for timing paths starting from registers and ending at latches

• Setup checks and hold checks for latch-to-reg timing paths - Discussed the default setup and hold checks for timing paths starting from latches and ending at registers

• All about clock signals - Discusses the basics of clock signals

• Synchronizers - Different types of synchronizers have been discussed in detail

• Timing corners - dimensions in timing signoff - Highlights the importance of signing off in different corner-case scenarios

• Ensuring glitch-free propagation of clock - Discusses about the hazards that can occur, if there is a glitch in clock

• Clock switching and clock gating checks - The basics of clock gating check, and how to apply these is discussed

• Clock gating checks at a mux - How clock gating checks should be applied on a mux is discussed in detail

• False paths - what are they - This post discussed the basics of false paths and how to treat them

• Multicycle paths handling in STA - Basics of multicycle paths and how they are treated in STA

• All about multicycle paths in VLSI - Architecture specific description and handling of multicycle paths, a must read

• Propagation delay - Defines propagation delay and related terms

• Is it possible for a logic gate to have negative delay - Thought provoking post on whether a logic gate can have negative delay

• Worst slew propagation - Discusses the basics of worst slew propagation

• On-chip variations - Describes on-chip variations and the methods undertaken to deal with these

• Temperature inversion - Discusses the concept of temperature inversion and conductivity trends with temperature

• Can a net have negative delay - Describes how a net cannot have a negative delay

• Timing arcs - Discusses the basics of timing arcs, positive and negative unateness, cell arcs and net arcs etc.

• Time borrowing in latches - Discusses the basics of the concept of time borrowing

• Interesting problem - latches in series - Describes why it is essential to have alternate positive and negative latches for sequential operation

• Virtual clock - Explains the concept of virtual clock

• Minimum pulse width - Discusses about minimum pulse width checks

• Basics of latch timing - Definition of latch, setup time and hold timing of a latch, latch timing arcs are discussed