What is time borrowing: Latches exhibit the property of being transparent when clock is asserted to a required value. In sequential designs, using latches can enhance performace of the design. This is possible due to time borrowing property of latches. We can define time borrowing in latches as follows:
Time borrowing is the property of a latch by virtue of which a path ending at a latch can borrow time from the next path in pipeline such that the overall time of the two paths remains the same. The time borrowed by the latch from next stage in pipeline is, then, subtracted from the next path's time.
The time borrowing property of latches is due to the fact that latches are level sensitive; hence, they can capture data over a range of times than at a single time, the entire duration of time over which they are transparent. If they capture data when they are transparent, the same point of time can launch the data for the next stage (of course, there is combinational delay from data pin of latch to output pin of latch).
Let us consider an example wherein a negative latch is placed between two positive edge-triggered registers for simplicity and ease of understanding. The schematic diagram for the same is shown in figure 1 below:
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| Figure 1: Negative level-sensitive latch between two positive edge-triggered registers |
Figure 2 below shows the clock waveform for all the three elements involved. We have labeled the clock edges for convenience. As is shown, latB is transparent during low phase of the clock. RegA and RegC (positive edge-triggered registers) can capture/launch data only at positive edge of clock; i.e., at Edge1, Edge3 or Edge5. LatB, on other hand, can capture and launch data at any instant of time between Edge2 and Edge3 or Edge4 and Edge5.
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| Figure 2: Clock waveforms |
The time instant at which data is launched from LatB depends upon the time at which data launched from RegA has become stable at the input of latB. If the data launched at Edge1 from RegA gets stable before Edge2, it will get captured at Edge2 itself. However, if the data is not able to get stable, even then, it will get captured. This time, as soon as the data gets stable, it will get captured. The latest instant of time this can happen is the latch closing edge (Edge3 here). One point here to be noted is that at whatever point data launches from LatB, it has to get captured at RegC at edge3. The more time latch takes to capture the data, it gets subtracted from the next path. The worst case setup check at latB is at edge2. However, latch can borrow time as needed. The maximum time borrowed, ideally, can be upto Edge3. Figure 3 below shows the setup and hold checks with and without time borrow for this case:
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| Figure 3: Setup check with and without time borrow |
The above example consisted of a negative level-sensitive latch. Similarly, a positive level-sensitive latch will also borrow time from the next stage, just the polarities will be different.
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Hi sir,
ReplyDeleteCan I say that we get required time is 1.5 clock cycle when there is path between positive triggered floo to positive latch..some where in internet they show this is possible.
Is it correct or wrong
Hi Kalyan
DeleteNo, I dont think what you are saying is correct. Can you share which link you are talking about. Maybe there are some architectural care-abouts too for this.
https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Time-Borrowing-in-Latches/ba-p/651529
DeleteYes If the middle latch is positive enabled, then the total path becomes 2 cycle instead of 1.
DeleteTherefore you can borrow uptil 1.5 cycles and next path could become 0.5 cycle
Yes, if the latch is positive triggered, then the total path becomes 2 cycles. Therefore you can borrow upto 1.5 cycles and next path will become 0.5 cycle
DeleteI dont agree with the concepts provided in the link you shared. A positive flop to latch path is half cycle, not 1.5 cycle.
DeleteHi sir,
ReplyDeleteBy default tool has setup check like
Set_multicycle_path 1 -end -setup...
So it might possible in this way
Hi
DeleteYes, they seem to have assumed "set_multicycle_path 2 -end -setup" for to_latch timing path because default setup check for pos_flop -> pos_latch path is zero cycle without time borrow and half cycle with max time borrow. But they have missed one basic thing of hold, which also moves along setup check, if not taken care by design. But for illustration purposes, their example is good.
Thank you sir...
DeleteHappy to help
DeleteHi,
ReplyDeleteIf you are going to capture the data at edge 3, then putting a latch in between will only add-up extra delay right?. Instead u can combine the combinational logic and give it directly to the reg C. What is the use of negative latch here then?
Hi
DeleteDelay will not be same for combinational logic accross all combinations of process, voltage and temperature. For correct state machine behavior, you need to ensure that data is captured always at the same edge as the state machine is designed for. This may not be true for purely data transfer cases, where data is transferred from one module to another. Here also, you need to ensure that there is no metastability. Hence, a latch is needed to ensure predictable delay in cases of PVT where the delay is less. I hope I was able to answer your query.
Hi Kalyan,
DeleteI too had a same doubt as just like you. Kindly go through this link https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Time-Borrowing-in-Latches/ba-p/651529
Hope the above link will provide you enough clarity.
There is no benefit here in adding negative latch in above example. All it will do is add delay. If data can be captured by latch before edge3 and next flop can capture data from latch at edge 3 then what is the use of latch. Even if you remove that latch , next flop will capture data at edge 3 if it is able to do it with latch.
DeleteHi,
ReplyDeleteAs I see in the standard cells, the setup and hold checks are happening at positive edge of a negative level latch.
So in the above example, the timing check is happening at negative edge for negative level latch.
I am thinking that above two statements are conflicting.
Can you let me know that is anything that I am missing?
Regards
A.Kotaiah
Hi
DeleteYes, you are right that textbooks teach what you are talking about and it is right too when a latch is implemented standalone. But when a latch is implemented in a system, it is convenient to assume it the way that has been mentioned in this post due to the concept of time borrowing only. In case of any queries, please let me know. I'll try to share in more detail.
Hi
ReplyDeleteI am investigating time borrowing method, but I don't know insert the latch in rtl code or synthesis, please help me. Thank you!
Hi
DeleteI assume you just want to explore the concepts and not implement the design. In that case, you can just replace a flip-flop in gate-level code by a latch.
Sir , If you launching at edge1 and capturing at edge3 , it is totally 1 clock cycle alone. Then what did you even borrow ? Time borrow means , a timing path gets more than 1 clock cycle to compute. for which there needs to be a positive sensitive latch inbetween. this negative latch inbetween will only give "hold protection" to RegC nothing else . Hold protection means, when hold check is performed at RegC , The latch is opaque. so a new data cannot come and corrupt the current sampled data as the latch is behaving like a WAll for half cycle. Thats the only benefit when you have negative latch between 2 flops. For time borrow , you need positive latch between 2 flops....
ReplyDeleteHi vn
DeleteSetup check from positive flop to positive latch is zero cycle, so there is no advantage of a positive latch here. Here, timing is being borrowed as positive flop to negative latch was half cycle and it can indeed take more than half cycle if there is positive slack in latch to flop path.
So.. Can you please clarify this for me?
ReplyDelete1. We need to use +ve level latch incase we want to solve the set-up time violation
2. We need to use -ve level latch incase we want to fix hold time issue
Is this correct ?
Hi, no this cannot be generalized. It is the relative position of latches that matters.
DeleteHi,Nice artical. Will pos level sensitive latch to pos level sensitive latch will give setup relaxation more than 1 cycle?
ReplyDeleteHi, under normal cases, it is not possible since you have to take care of hold itself. But having said that, you can always modify your state machine, like you do in case of flip-flops and achieve multi-cycle paths.
Delete