Divide by 2 clock in VHDL

Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequency as compared to input clock. A flip-flop with its inverted output fed back to its input serves as a divide-by-2 circuit. Figure 1 shows the schematic representation for the same.

Divide by 2 clock circuit

                                          

Following is the code for a divide-by-2 circuit.

-- This module is for a basic divide by 2 in VHDL.

library ieee;

use ieee.std_logic_1164.all;

entity div2 is

                port (

                                reset : in std_logic;

                                clk_in : in std_logic;

                                clk_out : out std_logic

                );

end div2;

-- Architecture definition for divide by 2 circuit

architecture behavior of div2 is
signal clk_state : std_logic;

begin

                process (clk_in,reset)

                begin

                                if reset = '1' then

                                                clk_state <= '0';

                                elsif clk_in'event and clk_in = '1' then

                                                clk_state <= not clk_state;

                                end if;

                end process;
clk_out <= clk_state;

end architecture;

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Design Quiz: multiply by 2 clock circuit

Design problem: Make a simple circuit whose output clock is twice in frequency to the input clock.

An XOR gate with one of its input getting delayed version of the other input can act as a frequency multiplier. Since, an XOR gate produces a ‘0’ when both inputs are same, and ‘1’ when both inputs are different; if it gets delayed version of one input at the other, every time input toggles, a pulse is produced at the output. The duration of the pulse is equal to the delay introduced by delay element. The circuit and the resulting waveform is shown in figure 1 below. This circuit arrangement is also known as pulse generator as it produces a pulse on every toggle of input.

(a) Multiply-by-2 clock circuit                                      (b) Input and output clock waveforms of multiply-by-2                                                                                                 clock circuit

Characteristics of XOR multiply by 2:

• The output pulse duration is equal to the delay introduced by delay element.
• For duty cycle to be equal to 50%, the delay element’s delay must be half that of input clock. Since, this cannot be guaranteed, the output duty cycle will not be 50%.
• The delay element’s delay must be less than half the input clock period; otherwise it will not work
• The inactive state of XOR multiply-by-2 will be 0 as it produces a '0' when both inputs are same. To implement a multiply-by-2 circuit with '1' as inactive state, you will have to use an XNOR gate.

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Also read:

• Designing a clock signal in VHDL
• Interesting design quiz - BCD multiply-by-5 circuit
• XOR/XNOR gate using 2:1 mux

XOR/XNOR gate using 2:1 MUX

2-input XOR gate using a 2:1 multiplexer: As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select input. The function of a 2:1 multiplexer can be given as:

OUT = IN0 when SEL = 0 ELSE IN1

Also, a 2-input XOR gate produces a ‘1’ at the output if both the inputs have different value; and ‘0’ if the inputs are same. The truth table of an XOR gate is given as:

A	B	OUT
0	0	0
0	1	1
1	0	1
1	1	0

Truth table of XOR gate

In the truth table of XOR gate, if we fix a value, say B, then

OUT = A WHEN B = 0 ELSE A’

Both the above equations seem equivalent if we connect negative of IN0 to IN1 in a multiplexer. This is how a 2:1 multiplexer will implement an XOR gate. Figure 1 below shows the implement of a 2-input XOR gate using a 2:1 Multiplexer.

Implementing a 2-input XOR gate using a 2:1 Multiplexer

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2-input XNOR gate using a 2:1 multiplexer: Similarly, the truth table of XNOR gate can be written as:

A	B	OUT
0	0	1
0	1	0
1	0	0
1	1	1

Truth table of XNOR gate

In the truth table, if we fix, say A, then

OUT = B WHEN A = 1, ELSE B’

Thus, XNOR gate is the complement of XOR gate. It can be implemented if we connect A to IN1 and Abar to IN0.

2-input XNOR gate using 2:1 multiplexer

Read also:

• Build a latch using 2:1 multiplexer
• Clock gating checks at a multiplexer
• Implementing 3 and 4 variable functions using a multiplexer
• Interesting Design problem - BCD multiply by 5 circuit

Latency and throughput – the two measures of system performance

Performance of the system is one of the most stringent criteria for its success. While performance increases the desirability among customers, cost is what makes it affordable. This is the reason why system designers aim for maximum performance with available resources such as power and area constraints. There are two related parameters that determine the performance output of a system –

Throughput - Throughput is a measure of the productivity of the system. In electronic/communication systems, throughput refers to rate at which output data is produced. Higher the throughput, more productive is the system. In most of the cases, it is measured as time difference between two consecutive outputs (nth and n+1th). Throughput also refers to the rate at which input data can be applied to system.

Let us discuss with the help of an example:

Above figure depicts the throughput of 3 number adder. Result of input set applied at 1st clock cycle appears at output at 3rd clock cycle and in 4th clock cycle next input set is applied and output comes in 6th clock cycle.  Hence, throughput of above design is ⅓ per clock cycle. As we can see from diagram, first input is applied in first clock cycle and 2nd input is applied in 4th clock cycle. Hence we can also say that throughput is rate at which input data can be applied to system.

Latency- Latency is the time taken by a system to produce output after input is applied. It is a measure of delay response of a design. Higher the latency value, slower is the system. in synchronous designs, it is measured in terms of number of clock cycles. In combinational designs, latency is basically propagation delay of circuit. In non pipelined designs, latency improvement is major area of concern. In more general terms, it is time difference between output and input time.

Relationship between throughput and latency: Both latency and throughput are inter-related. It is desired to have maximum throughput and minimum latency. Increasing latency and/or throughput might make the system costly. Let us take an example. Consider a park with 3 rides and it takes 5 minutes for a ride.  A child can take sequentially these rides; i.e, ride 1, ride 2 and then ride 3. Firstly, let us assume that only one child at a time is allowed to enter park at a time. While he is taking a ride, no one is allowed to enter the park. Thus, the throughput of the park is 15 minutes per child and latency is 15 minutes. Now, let us assume that while a child has finished taking ride1, another child is allowed to enter park. Thus, in this case, throughput will be 5 minutes per child whereas latency is still 15 minutes. Thus, we have increased the throughput of the system without affecting latency and at the same cost.

Digital Counters

Digital Counters, as the name suggests, are digital circuits used for counting occurrence of any event. For any digital system like a computer, counters are most useful and versatile subsystem. A flip-flop can be used as a counter to count two states since Flip flop has two states either 0 or 1. Similarly, two flip-flops can be connected together to count 4 states (00, 01, 10, 11). Thus, with n flip-flops, we can make a counter that can count maximum 2ⁿ stages . Digital counters have following properties:

1)      Asynchronous or Synchronous – Asynchronous counters are one in which output of one flip-flop drives succeeding FF. Only first FF needs clock. All other Flops will be driven by its preceding FF. While in synchronous counters All FF are clocked by same external clock pulse.    

2)      Maximum number of counts – Also known as Modulus of counter. Modulus of counter is equal to total number of distinct stages through which counter progresses. For example:  A 4 Flip flop counter is often referred to as mod-16 counter i.e it can count 16 stages.

3)      Up or down counter – It dictates whether counter counts in upward or downward direction. For exp . 0 ->1->2->3->4->5->6->7 is up counter. 7->6->5->4->3->2->1->0 is down counter. The counter which can count in up or down direction depending upon some external signal(e.g.  if up(some external signal) is 1, count in upward direction else in downward) is called up-down counter.

4)      Free running or self stopping – if counter begins counting again after reaching its maximum stage,counter is called free running and if it stops after reaching maximum stage value it is called self stopping. Free running counters are also known as blind running counters.

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Implement 3 and 4 variable function using 8:1 MUX

Three variable  function can be easily implemented using 8:1 multiplexer. connect 3 input lines to select lines of mux and connect 8 inputs of mux to logic 0 or 1 according to function output. For example, let us say Function is

                                      F(X,Y,Z) = Σ(0,1,3,6)

then X,Y,Z will be connected to select lines of Mux and I0 , I1, I3 and I6 will be connected to logic 1(VDD) and other will be connected to logic 0

For a 4 variable function, there are 16 possible combinations. To implement 4 variable function using 8:1 MUX, use 3 input as select lines of MUX and remaining 4th input and function will determine ith input of mux . Let us demonstrate it with an example :

                                  F(A,B,C,D) = Σ(1,5,7,9,10,11,12)

A	B	C	D	Decimal Equivalent	F
0	0	0	0	0	0
1	0	0	0	8	0
0	0	0	1	1	1
1	0	0	1	9	1
0	0	1	0	2	0
1	0	1	0	10	1
0	0	1	1	3	0
1	0	1	1	11	1
0	1	0	0	4	0
1	1	0	0	12	1
0	1	0	1	5	1
1	1	0	1	13	0
0	1	1	0	6	0
1	1	1	0	14	0
0	1	1	1	7	1
1	1	1	1	15	0

The 4 variable function represented using 8:1 mux

                                  ABar = ~A (inverted A)

As shown in figure, B,C,D are used as select lines and A will be used input  of Mux. from Truth table, if B,C,D  are 0 then output F is 0 irrespective of status of A so I0 = 0. For I5(BCD = 101) output depend upon A.

                                     for A = 0,  F  = 1
                                     for A = 1,  F =  0
                          Hence F = ~A (for BCD = 101)
                                    I4, (B = 1, C = 0, D = 0),  F = A
                                    I1, (B = 0, C =  0,D  = 1), F = 1 (irrespective of status of A)

similarly All other inputs can be inferred in the same way.  Thus we can conclude that to implement n variable function, we need 2^(n-1) to 1 MUX and an inverter. n-1 input lines shall be used as select lines and rest one will be used for input of MUX.

Also read:

• Binary to thermometer encoder
• Clock gating checks at a multiplexer
• Lockup latch - principle and application
• Carry look ahead adder
• Interesting problem - BCD multiply by 5 circuit

Analog to Digital Converter

In real world, all signals like light, sound etc, are analog signals. These signals have to be converted into digital form so that they can be manipulated by digital equipment. Device used to convert analog signal into digital signal is called Analog to Digital Converter (ADC). An example of an analog to digital converter is a Scanner – It takes a picture (analog) as input and convert into digital picture. ADC is an electrical circuit that converts continuous time and continuous amplitude signal into discrete time and discrete amplitude signal.

Let us first discuss basic concept of analog to digital conversion. The process of digitizing the domain(time) is called sampling and the process of digitizing range(voltage/current) is called quantization.

Sampling : An ADC circuit samples analog signal from time to time. Then, each sample is converted into a number based on its voltage level. The frequency at which sampling occurs is called sampling rate or sampling frequency. e.g if sampling frequency is 22000 Hz, it means, in one second 22000 input points will be sampled and distance between two adjacent time points is 1/22000 seconds. Higher the sampling frequency, more perfect will be the analog signal produced by DAC (when it is required to reconstruct the analog signal from digital samples). But more memory will be needed to store these samples. So there is always a trade off between memory required to store samples and accuracy of signal. But to reproduce analog signal from digital samples, there should be some minimum number of samples. And

According to Nyquist sampling theorem, sampling rate must be at least twice the highest frequency component to avoid aliasing.

                                      Fs = 2Fmax

Quantization: Quantization is the process of converting continuous value signal into discrete value signal so that signal takes only finite set of values. Unlike sampling (where we saw that under some conditions, it is possible to reconstruct the signal), quantization results in some loss of information called quantization error. One of basic choice in quantization is the number of discrete quantization levels to use. Fundamental tradeoff in this choice is the resulting signal quality vs data(bits) needed to represent each sample. With L levels, number of bits required to represent each level,

                     
              N = logL/log2.

Analog to Digital Converter with 32 levels(5 bits)

Power aware RTL design

With the progress in technology, the designs are moving into deeper sub-micron technology nodes. There is an ever-increasing concern about power dissipation within the SoC. But this should not come at the cost of performance. So, along with less power dissipation, there is need for maximum power efficiency, that is maximum proportion of available power should be used for useful purposes rather than just to keep the device awake. Now the question arises: Whether to start planning from power perspective at the RTL Design level or wait for the problems to be fixed in the backend flow of the design cycle. The answer is former. Efforts are made to achieve maximum power efficiency along all the stages of the design. But the backend flow can only implement the changes at physical level. It cannot fix the micro-architecture which has a significant impact on the dynamic power dissipation within the SoC.

Figure showing Impact of design change on performace

Power aware design is achieved at several levels of abstraction. System design starts from system requirements and specification and goes through design at architecture design, RTL design, gate level design and finally, layout design. At all these stages, techniques are adopted to meet the design power and performance requirements. It has been found that any effort that is made to improve the power efficiency along all the design stages has maximum impact, if it is done at the RTL level. But, the impact is measured most immediately if it is done at the layout level. So, it is very difficult to measure the impact of any architectural change at RTL level. Improvements are needed for power estimation methods at the RTL level. But, it does not mean that backend techniques should not be adopted.

Power aware design is often misunderstood as low power design. But, these are not the same. By low power design, we mean minimizing the power consumption with or without any performance constraint. But by power aware design, is meant the minimizing the power dissipation without any impact on power. Power aware design refers to maximizing some other performance constraint without any significant impact on power efficiency. Achieving maximum performance being constrained to a particular power budget is the aim of power aware design. 

As said earlier, there is an ever increasing demand for low power devices. As these devices run on batteries having limited supply, and the requirement for them is to operate the maximum they can on a single battery. There are long phases of device idle time. In between, the device is active for very small periods of time. And during the active time, high performance is the requirement. One such example is digital energy meters where there is requirement to keep record of the total kWh used. The power may be available in patches, or may be continuously available. There may be long periods when there is no power. Since the power is available, we can afford to have chargeable batteries, but the watts consumed by the controller itself should be very less as compared to the total power consumed so as to minimize the overhead. During the idle periods, device may go to sleep mode so as to save power. As long as power is available, it should wake up immediately. In other words, average power is less but variance in power consumption is very high.  Hence, it requires a provision in RTL to sense incoming signal levels and to change the gears accordingly. There are many techniques adopted for power aware RTL designsuch as performance throttling, judicious module selection, incorporation of power information in RTL, voltage and power islands and power aware design of memories.

Read also:

• Why depletion MOS cannot be used to create negative logic
• Transmission gates
• Synchronization schemes in VLSI design
• Race conditions
• Our world - digital or analog