Showing posts with label XNOR using NAND gates. Show all posts
Showing posts with label XNOR using NAND gates. Show all posts

XNOR gate using NAND

As we know, the logical equation of a 2-input XNOR gate is given as below:
                      Y = A (xnor) B = (A' B '   +    A B)
Let us take an approach where we consider and A' as different variables for now (optimizations related to this, if any, will consider later). Thus, the logic equation, now, becomes:
                       Y = (CD    +    A B)           -----   (i)
     where
                      C = A'     and      D = B'
De-Morgan's law states that
                                m + n = (m'n')'

Taking this into account,
                     Y = ((CD)'(AB)')' = ((A' B')'  (A B)')'
Thus, Y is equal to ((A' nand B') nand (A nand B)). No further optimizations to the logic seem possible to this logic. Figure 1 below shows the implementation of XOR gate using 2-input NAND gates.
A 2 -input XOR gate implementation using NAND, XOR gate using NAND
Figure 1: 2-input XNOR gate implementation using NAND gates