Timing Corners – dimensions in timing signoff

Integrated circuits are designed to work for a range of temperatures and voltages, and not just for a single temperature and voltage. These have to work under different environmental conditions and different electrical setup and user environments. For instance, the temperature in the internals of an automobile may reach as high as 150 degrees while operating. Also, automobiles may have to work in colder regions where temperatures may reach -40 degrees during winters. So, a chip designed for automobiles has to be designed so as to be able to work in temperatures ranging from -40 to 150 degree Celsius. On the other hand, consumer electronics may have to work in the range of -20 to +40 degrees only. Thus, depending upon the application, the chip has to be robust enough to handle varying surrounding temperatures. Not just surrounding temperatures, the voltage supplied by the voltage source may vary. The battery may have an output voltage range. Also, the voltage regulator sitting inside or outside the chip may have some inaccuracy range defined. Let us say, a SoC has a nominal operating voltage of 1.2V with 10% variation. Thus, it can operate at any voltage from 1.08 V to 1.32V. The integrated circuits have to be tolerable enough to handle these variations. Not just these variations, the process by which the integrated circuits are manufactured has variations due to its micro nature. For example, while performing etching, the depth of etching may vary from wafer to wafer, and from die to die. Similarly, doping, width of wires drawn, distance between wires may vary for each wire from chip-to-chip. Depending upon these, the behavior (delay, static and dynamic power consumption etc) of cells on chip vary. These variations are together referred as PVT (Process Voltage Temperature) variations. The behavior of the devices also varies according to the PVT variations. The library (liberty) models of the cells are characterized for cell delays, transitions, static and dynamic power corresponding to different PVT combinations. Not just for cells, for nets too, these variations are possible. The net parameters (resistance, capacitance and inductance) may also vary. These parameters also account for cell delay. In addition, nets introduce delay of their own too. Hence, one may get nets with high or less delay. So, these variations also have to be taken into account for robust integrated circuit manufacture. This variation in net characteristic can be modeled as their RC variation as it accounts for changes in resistance and capacitance (ignoring inductance) of net.

Figure 1: A racing car. (Taken from en.wikipedia.com)

With proper techniques, the patterns of the variations for both the cell and net parameters (delay, power, resistance and capacitance) are characterized and their minima and maxima are recorded. Each minima and maxima can be termed as a corner. Let us say, each minima/maxima in cell characteristics as ‘PVT corner’ and net characteristics as ‘extraction corner’.  Each combination of PVT extraction corners is referred to as a ‘timing corner’ as it represents a point where timing will be extreme. There is an assumption that if the setup and hold conditions are met for the design at these corners, these will be met at intermediate points and it will be safe to run under all conditions. This is true in most of the cases, not always. There is always a trade-off between number of signed-off corners and the sign-off quality.

 

For bigger technologies, say 250 nm, only two corners used to be sufficient, one that showed maximum cell delay and the other that showed least cell delay. Net variations could be ignored for such technologies. In all, there used to be 2 PVT and 1 extraction corner.  As we go down technology nodes, net variations start coming into picture. Also, cell characteristics do not show a linear behavior. Therefore, there is increased number of PVT as well as extraction corners for lower technology nodes. For 28 nm, say, there can be 8 PVT corners as well 8 extraction corners. The number of corners differs from foundry to foundry.  The chip has to be signed off in each and every corner to ensure it works in every corner. However, we may choose to sign-off in lesser corners with applying some extra uncertainty as margin in lieu of not signing off at these timing corners. The timing analyst needs to decide what is appropriate depending upon the resources and schedule.

Also read:

• All about clock signals
• Is it possible for a logic gate to have negative delay
• Why depletion MOS cannot be used to create negative logic
• Propagation delay