Divide by 2 clock in VHDL

Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequency as compared to input clock. A flip-flop with its inverted output fed back to its input serves as a divide-by-2 circuit. Figure 1 shows the schematic representation for the same.

Divide by 2 clock circuit

                                          

Following is the code for a divide-by-2 circuit.

-- This module is for a basic divide by 2 in VHDL.

library ieee;

use ieee.std_logic_1164.all;

entity div2 is

                port (

                                reset : in std_logic;

                                clk_in : in std_logic;

                                clk_out : out std_logic

                );

end div2;

-- Architecture definition for divide by 2 circuit

architecture behavior of div2 is
signal clk_state : std_logic;

begin

                process (clk_in,reset)

                begin

                                if reset = '1' then

                                                clk_state <= '0';

                                elsif clk_in'event and clk_in = '1' then

                                                clk_state <= not clk_state;

                                end if;

                end process;
clk_out <= clk_state;

end architecture;

Hope you’ve found this post useful. Let us know what you think in the comments.

Design Quiz: multiply by 2 clock circuit

Design problem: Make a simple circuit whose output clock is twice in frequency to the input clock.

An XOR gate with one of its input getting delayed version of the other input can act as a frequency multiplier. Since, an XOR gate produces a ‘0’ when both inputs are same, and ‘1’ when both inputs are different; if it gets delayed version of one input at the other, every time input toggles, a pulse is produced at the output. The duration of the pulse is equal to the delay introduced by delay element. The circuit and the resulting waveform is shown in figure 1 below. This circuit arrangement is also known as pulse generator as it produces a pulse on every toggle of input.

(a) Multiply-by-2 clock circuit                                      (b) Input and output clock waveforms of multiply-by-2                                                                                                 clock circuit

Characteristics of XOR multiply by 2:

• The output pulse duration is equal to the delay introduced by delay element.
• For duty cycle to be equal to 50%, the delay element’s delay must be half that of input clock. Since, this cannot be guaranteed, the output duty cycle will not be 50%.
• The delay element’s delay must be less than half the input clock period; otherwise it will not work
• The inactive state of XOR multiply-by-2 will be 0 as it produces a '0' when both inputs are same. To implement a multiply-by-2 circuit with '1' as inactive state, you will have to use an XNOR gate.

Hope you’ve found this post useful. Let us know what you think in the comments.

Also read:

• Designing a clock signal in VHDL
• Interesting design quiz - BCD multiply-by-5 circuit
• XOR/XNOR gate using 2:1 mux

Delay line based Time to digital converter

A time to digital converter is a circuit that digitizes time; i.e., it converts time into digital number. In other words, a time-to-digital converter measures the time interval between two events and represents that interval in the form of a digital number.

TDCs are used in places where the time interval between two events needs to be determined. These two events may, for example, be represented by rising edges of two signals. Some applications of TDCs include time-of-flight measurement circuits and All-Digital PLLs.

Delay line based time-to-digital converter: This is a very primitive TDC and involves a delay-line which is used to delay the reference signal. The other signal is used to sample the state of delay chain. Each stage of delay chain outputs to a flip-flop or a latch which is clocked by the sample signal. Thus, the output of the TDC forms a thermometer code as the stage will show a ‘1’ if the reference signal has passed it, otherwise it will show a zero. The schematic diagram of delay line based time-to-digital converter is shown in figure 1 below:

Figure 1: Delay line based Time-to-digital converter

The VHDL code for delay line based time-to-digital converter is given below:

-- This is the module definition of delay line based time to digital converter.

library ieee;

use ieee.std_logic_1164.all;        

entity tdc is

                generic (

                                number_of_bits : integer := 64

                );

                port (

                                retimed_clk : in std_logic;

                                variable_clk : in std_logic;

                                tdc_out : out std_logic_vector (number_of_bits-1 downto 0);

                                reset : in std_logic

                );

end entity;

architecture behavior of tdc is

                component buffd4 is port (

                                I : in std_logic;

                                Z : out std_logic

                );

                end component;

                signal buf_inst_out : std_logic_vector (number_of_bits downto 0);

begin

--buffd4

                buf_inst_out(0) <= variable_clk;

                tdc_loop : for i in 1 to (number_of_bits) generate

                begin

                                buf_inst : buffd4 port map (

                                                I => buf_inst_out(i-1),

                                                Z => buf_inst_out(i)

                                );

                end generate;

                process (reset,retimed_clk)

                begin

                                if reset = '1' then

                                                tdc_out <= (others => '0');

                                elsif retimed_clk'event and retimed_clk = '1' then

                                                tdc_out <= buf_inst_out(number_of_bits downto 1);

                                end if;

                end process;

end architecture;

References:

• Time-to-digital converter basics - Springer

Hope you’ve found this post useful. Let us know what you think in the comments.

Power aware RTL design

With the progress in technology, the designs are moving into deeper sub-micron technology nodes. There is an ever-increasing concern about power dissipation within the SoC. But this should not come at the cost of performance. So, along with less power dissipation, there is need for maximum power efficiency, that is maximum proportion of available power should be used for useful purposes rather than just to keep the device awake. Now the question arises: Whether to start planning from power perspective at the RTL Design level or wait for the problems to be fixed in the backend flow of the design cycle. The answer is former. Efforts are made to achieve maximum power efficiency along all the stages of the design. But the backend flow can only implement the changes at physical level. It cannot fix the micro-architecture which has a significant impact on the dynamic power dissipation within the SoC.

Figure showing Impact of design change on performace

Power aware design is achieved at several levels of abstraction. System design starts from system requirements and specification and goes through design at architecture design, RTL design, gate level design and finally, layout design. At all these stages, techniques are adopted to meet the design power and performance requirements. It has been found that any effort that is made to improve the power efficiency along all the design stages has maximum impact, if it is done at the RTL level. But, the impact is measured most immediately if it is done at the layout level. So, it is very difficult to measure the impact of any architectural change at RTL level. Improvements are needed for power estimation methods at the RTL level. But, it does not mean that backend techniques should not be adopted.

Power aware design is often misunderstood as low power design. But, these are not the same. By low power design, we mean minimizing the power consumption with or without any performance constraint. But by power aware design, is meant the minimizing the power dissipation without any impact on power. Power aware design refers to maximizing some other performance constraint without any significant impact on power efficiency. Achieving maximum performance being constrained to a particular power budget is the aim of power aware design. 

As said earlier, there is an ever increasing demand for low power devices. As these devices run on batteries having limited supply, and the requirement for them is to operate the maximum they can on a single battery. There are long phases of device idle time. In between, the device is active for very small periods of time. And during the active time, high performance is the requirement. One such example is digital energy meters where there is requirement to keep record of the total kWh used. The power may be available in patches, or may be continuously available. There may be long periods when there is no power. Since the power is available, we can afford to have chargeable batteries, but the watts consumed by the controller itself should be very less as compared to the total power consumed so as to minimize the overhead. During the idle periods, device may go to sleep mode so as to save power. As long as power is available, it should wake up immediately. In other words, average power is less but variance in power consumption is very high.  Hence, it requires a provision in RTL to sense incoming signal levels and to change the gears accordingly. There are many techniques adopted for power aware RTL designsuch as performance throttling, judicious module selection, incorporation of power information in RTL, voltage and power islands and power aware design of memories.

Read also:

• Why depletion MOS cannot be used to create negative logic
• Transmission gates
• Synchronization schemes in VLSI design
• Race conditions
• Our world - digital or analog