Problem: Consider a complex gate with internal structure as shown in figure below. One of the inputs gets clock while all others get data signals. What all (and what type of) clock gating checks exist?
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| Figure:Problem figure |
Solution: As we know, clock gating
checks can be of AND type or OR type. We can find the type of clock gating
check formed between a data and a clock signal by considering all other signals
as constant. Since, all the 4 data signals control Clk in one or the other way, there are following clock gating
checks formed:
i)
Clock
gating check between Data1 and Clk: As is evident, invert of Clk and Data1 meet at OR gate ‘6’. Hence, there is OR type check between invert of Clk and Data1. In other words, Data1
can change only when invert of Clk is high or Clk is low. Hence, there is AND
type check formed at gate 6.
ii)
Clock
gating check between Data2 and Clk: Same as in case 1.
iii)
Clock
gating check between Data3 and Clk: There is AND type check between Data3 and Clk.
iv)
Clock
gating check between Data4 and CLK: As in 1 and 2, there is AND type check between Data4 and Clk.
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