Clock dividers
are ubiquitous circuits used in every digital design. A divide-by-N divider
produces a clock that is N times lesser frequency as compared to input clock. A
flip-flop with its inverted output fed back to its input serves as a
divide-by-2 circuit. Figure 1 shows the schematic representation for the same.
Divide by 2 clock circuit |
Following is the
code for a divide-by-2 circuit.
-- This module is for a
basic divide by 2 in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity div2 is
port (
reset : in std_logic;
clk_in : in std_logic;
clk_out : out std_logic
);
end div2;
-- Architecture definition for divide by 2 circuit
architecture behavior of div2
is
signal clk_state : std_logic;
signal clk_state : std_logic;
begin
process (clk_in,reset)
begin
if reset = '1' then
clk_state <= '0';
elsif clk_in'event and clk_in = '1'
then
clk_state <= not
clk_state;
end if;
end process;
clk_out <= clk_state;
clk_out <= clk_state;
end architecture;
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