Showing posts with label Net delay. Show all posts
Showing posts with label Net delay. Show all posts

Propagation delay of a net

Definition of net propagation delay: The propagation delay of a net can be defined as the amount of time it takes a logic signal to propagate from the output of one logic gate to the input of another. Normally, it is defined as the difference between the times when the output of driver gate of net reaches 50% of its final value to when the input of the load cell of net reaches 50% of its final value.

How net delay is calculated: The net delay is calculated from the parasitics of the net. The parasitics are calculated based upon the topology of the net. These may also be read in from the parasitics file (SPEF, DSPF etc). The resulting RC-circuit resulting from the net topology is, then, simulated using certain algorithms (cosidering speed and accuracy requirements) for net delay.