Problem: Derive the logical expression for a 4-bit increment by 2 circuit and draw the architecture of it.
Solution: The task here is to design a circuit that increments its count by two. Since, it is a 4-bit circuit, the total number of possible states is 16. Each state transitions to the state which has a binary value two greater than it. Now, there are two possible scenarios based upon the initial state that the counter gets into:
1. It can count 0 -> 2 -> 4 -> 6 -> 8 -> 10 -> 12 -> 14 -> 0 (their binary equivalents)
2. It can count 1 -> 3 -> 5 -> 7 -> 9 -> 11 -> 13 -> 15 -> 1 (their binary equivalents)
The state transition table can be represented as shown below:
We can find the expression for outputs using K-maps as below.
Expression for D3(next): Let us first derive the expression for D3(next). The K-map can be represented as below:
The expression for D3(next) as derived from K-map is:
Expression for D2(next): Given below is the K-map derived from state transition table for D2(next).
The expression for D2(next) as derived from K-map is:
Expression for D1(next): Given below is the K-map derived from state transition table for D1(next).
The expression for D1(next) is derived from K-map as:
Expression for D0(next): Given below is the K-map for D0(next).
The expression for D0(next) is:
Combining all the expressions, the circuit is as given below:
Can you come up with a better solution for this problem? Let us know your views in comments.
This question was asked by one Himadri Roy Pramanik on our post your query page. You can also post your queries there. We will try to answer using our limited knowledge.
Solution: The task here is to design a circuit that increments its count by two. Since, it is a 4-bit circuit, the total number of possible states is 16. Each state transitions to the state which has a binary value two greater than it. Now, there are two possible scenarios based upon the initial state that the counter gets into:
1. It can count 0 -> 2 -> 4 -> 6 -> 8 -> 10 -> 12 -> 14 -> 0 (their binary equivalents)
2. It can count 1 -> 3 -> 5 -> 7 -> 9 -> 11 -> 13 -> 15 -> 1 (their binary equivalents)
The state transition table can be represented as shown below:
We can find the expression for outputs using K-maps as below.
Expression for D3(next): Let us first derive the expression for D3(next). The K-map can be represented as below:
D3(next) = D3.D2' + D3.D1' + D3'.D2.D1
D3(next) = D3.(D2'+D1') + D3'.D2.D1.
D3(next) = D3.(D2.D1)'+D3'.(D2.D1)
D3(next) = D3 (exor) (D2.D1)
Expression for D2(next): Given below is the K-map derived from state transition table for D2(next).
D2(next) = D2'.D1 + D2.D1' = D2 (exor) D1
Expression for D1(next): Given below is the K-map derived from state transition table for D1(next).
D1(next) = D1'
Expression for D0(next): Given below is the K-map for D0(next).
D0(next) = D0
Combining all the expressions, the circuit is as given below:
Can you come up with a better solution for this problem? Let us know your views in comments.
This question was asked by one Himadri Roy Pramanik on our post your query page. You can also post your queries there. We will try to answer using our limited knowledge.