How to build an XOR gate using NAND gates

We can build a 2-input XOR gate using 5 NAND gates. Sound interesting, isn't it? Let us see how.

As we know, the logical equation of a 2-input XOR gate is given as below:

                      Y = A (xor) B = (A' B    +    A B')

Let us take an approach where we consider A and A' as different variables for now (optimizations related to this, if any, will consider later). Thus, the logic equation, now, becomes:

                       Y = (CB    +    A D)           -----   (i)

     where

                      C = A'     and      D = B'

De-Morgan's law states that

                                m + n = (m'n')'

Taking this into account,

                     Y = ((CB)'(AD)')' = ((A' B)'  (A B')')'

Thus, Y is equal to ((A' nand B) nand (A nand B')). No further optimizations to the logic seem possible to this logic. Figure 1 below shows the implementation of XOR gate using 2-input NAND gates.

Figure 1: 2-input XOR gate implementation using 2-input NAND gate

Thus, we have seen an XOR gate can be implemented by putting NAND gates in cascade. Can you think of a better way of implementing XOR gate using NAND gates?


Also read:

• XOR/XNOR gate using 2:1 mux
• Latch using 2:1 mux
• 2-input gates using 2:1 mux
• VHDL code for clock divider