Clock gating checks at a multiplexer (MUX)

In the post 'clock switching and clock gating checks', we discussed why clock gating checks are needed. Also, we discussed the two basic types of clock gating checks. Let us go one step further. The most common types of combinational cells with dynamic clock switching encountered in today’s designs are multiplexers. We will be discussing the clock gating checks at a multiplexer. For simplicity, let us say, we have a 2-input multiplexer with 1 select pin. There can be two cases:

Case 1: Data signal at the select pin of MUX used to select between two clocks

Mux with Data signal used to select clock to propagate to output
Figure 1: MUX with Data as select dynamically selecting the clock signal to propagate to output

This scenario is shown in figure 1 above. This situation normally arises when ‘Data’ acts as clock select and dynamically selects which of the two clocks will propagate to the output. The function of the MUX is given as:
CLK_OUT = Data.CLK1 + Data’.CLK2

The internal structure (in terms of basic gates) is as shown below in figure 2.

CLK_OUT = Data.CLK1 + Data’.CLK2
Figure 2: Internal structure of mux in figure 1

There will be two clock gating checks formed:

  1. Between CLK1 and Data: There are two cases to be considered for this scenario:
    • When CLK2 is at state '0': In this scenario, if the data toggles when CLK1 is '0', it will pass without any glitches. On the other hand, there will be a glitch if data toggles when CLK1 is '1'. Thus, the mux acts as AND gate and there will be AND-type clock gating check.
    • When CLK2 is '1': In this scenario, if data toggles when CLK1 is '1', it will pass without any glitches; and will produce a glitch if toggled when CLK1 is '0'. In other words, MUX acts as an OR gate; hence, OR-type clock gating check will be formed in this case.

  1. 2. Between CLK2 and Data: This scenario also follows scenario '1'. And the type of clock gating check formed will be determined by the state of inactive clock.

    1. Thus, the type of clock gating check to be applied, in this case, depends upon the inactive state of the other clock. If it is '0', AND-type check will be formed. On the other hand, if it is '1', OR-type check will be formed.
Case 2: Clock signal is at select line. This situation is most common in case of Mux-based configurable clock dividers wherein output clock waveform is a function of the two data values.

Mux with clock as select
Figure 3: Combination of Data1 and Data2 determines if CLK or CLK' will propagate to the output

In this case too, there will be two kinds of clock gating checks formed:

i)                  Between CLK and Data1: Here, both CLK and Data1 are input to a 2-input AND gate, hence, there will be AND type check between CLK and Data1. The following SDC command will serve the purpose:
set_clock_gating_check -high 0.1 [get_pins MUX/Data1]
The above command will constrain an AND-type clock gating check of 100 ps on Data1 pin.

ii)                    Between CLK and Data2: As is evident from figure 3, there will be AND type check between CLK’ and Data2. This means Data2 can change only when CLK’ is low. In other words, Data2 can change only when CLK is high. This means there is OR type check between CLK and Data2. The following command will do the job:
set_clock_gating_check -low 0.1 [get_pins MUX/Data2]
The above command will constrain an  OR-type clock gating check of 100 ps on Data2 pin.

Thus, we have discussed how there are clock gating checks formed between different signals of a MUX. 

8 comments:

  1. Figure4 is absent.Please add it.Nice article

    ReplyDelete
    Replies
    1. Hi

      It actually meant figure 3, corrected the typo. Thanks for your feedback.

      Delete
  2. Hi
    can you please explain why you are taking with reference to clk2 in case1 for checking between clk1 and data?

    ReplyDelete
    Replies
    1. Hi

      There are two different gates in path of clk1. For different values of clk2, the effect of one of the gates propagates.

      Delete
  3. nice article .can you please explain how clock gating will reduce dynamic power dissipation?

    ReplyDelete
    Replies
    1. Hi

      I have tried to explain at below link. We can discuss in case of any doubts.

      https://vlsiuniverse.blogspot.com/2020/03/how-clock-gating-reduces-power.html

      Delete
  4. In the case 1, where data is used to select the clocks CLK1,CLK2. Basically we encounter with four combinations of CLK1/2, for 00, no glitch propagation, for 01, OR clock gate check, 10 And clock gate Check. For case 11 since the Data is changing when clock is high so AND clock gating should be checked for this combination. Could you please comment on CLK1=CLK2=1 and if Data changes?

    ReplyDelete
    Replies
    1. Hi Yathish

      Iappreciate your thinking, but since both D0 & D1 are at value 1, the transition at output will be 1 -> 1, so there will not be any glitch under normal circumtances the same way as 00.

      However, there is a special case which can cause glitch here, if the propagation delay from D0 to OUT & D1 to OUT is not equal.

      Delete

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