2x1 mux using NAND gates

As we know, the logical equation of a 2-input mux is given as below:
                      Y = (s' A   +    s B)
Where s is the select of the multiplexer.
De-Morgan's law states that
                                m + n = (m'n')'

Taking this into account, here m = s'A  and  n = sB
                     Y = ((s'A)'(sB)')' = ((s' A)'  (s B)')'
Thus, Y is equal to ((s' nand A) nand (s nand B)). No further optimizations seem possible to this logic. Figure 1 below shows the implementation of 2:1 mux using 2-input NAND gates.
Figure 1: 2:1 Mux using NAND gates

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