Timing Corners – dimensions in timing signoff

Integrated circuits are designed to work for a range of temperatures and voltages, and not just for a single temperature and voltage. These have to work under different environmental conditions and different electrical setup and user environments. For instance, the temperature in the internals of an automobile may reach as high as 150 degrees while operating. Also, automobiles may have to work in colder regions where temperatures may reach -40 degrees during winters. So, a chip designed for automobiles has to be designed so as to be able to work in temperatures ranging from -40 to 150 degree Celsius. On the other hand, consumer electronics may have to work in the range of -20 to +40 degrees only. Thus, depending upon the application, the chip has to be robust enough to handle varying surrounding temperatures. Not just surrounding temperatures, the voltage supplied by the voltage source may vary. The battery may have an output voltage range. Also, the voltage regulator sitting inside or outside the chip may have some inaccuracy range defined. Let us say, a SoC has a nominal operating voltage of 1.2V with 10% variation. Thus, it can operate at any voltage from 1.08 V to 1.32V. The integrated circuits have to be tolerable enough to handle these variations. Not just these variations, the process by which the integrated circuits are manufactured has variations due to its micro nature. For example, while performing etching, the depth of etching may vary from wafer to wafer, and from die to die. Similarly, doping, width of wires drawn, distance between wires may vary for each wire from chip-to-chip. Depending upon these, the behavior (delay, static and dynamic power consumption etc) of cells on chip vary. These variations are together referred as PVT (Process Voltage Temperature) variations. The behavior of the devices also varies according to the PVT variations. The library (liberty) models of the cells are characterized for cell delays, transitions, static and dynamic power corresponding to different PVT combinations. Not just for cells, for nets too, these variations are possible. The net parameters (resistance, capacitance and inductance) may also vary. These parameters also account for cell delay. In addition, nets introduce delay of their own too. Hence, one may get nets with high or less delay. So, these variations also have to be taken into account for robust integrated circuit manufacture. This variation in net characteristic can be modeled as their RC variation as it accounts for changes in resistance and capacitance (ignoring inductance) of net.

Figure 1: A racing car. (Taken from en.wikipedia.com)

With proper techniques, the patterns of the variations for both the cell and net parameters (delay, power, resistance and capacitance) are characterized and their minima and maxima are recorded. Each minima and maxima can be termed as a corner. Let us say, each minima/maxima in cell characteristics as ‘PVT corner’ and net characteristics as ‘extraction corner’.  Each combination of PVT extraction corners is referred to as a ‘timing corner’ as it represents a point where timing will be extreme. There is an assumption that if the setup and hold conditions are met for the design at these corners, these will be met at intermediate points and it will be safe to run under all conditions. This is true in most of the cases, not always. There is always a trade-off between number of signed-off corners and the sign-off quality.

 

For bigger technologies, say 250 nm, only two corners used to be sufficient, one that showed maximum cell delay and the other that showed least cell delay. Net variations could be ignored for such technologies. In all, there used to be 2 PVT and 1 extraction corner.  As we go down technology nodes, net variations start coming into picture. Also, cell characteristics do not show a linear behavior. Therefore, there is increased number of PVT as well as extraction corners for lower technology nodes. For 28 nm, say, there can be 8 PVT corners as well 8 extraction corners. The number of corners differs from foundry to foundry.  The chip has to be signed off in each and every corner to ensure it works in every corner. However, we may choose to sign-off in lesser corners with applying some extra uncertainty as margin in lieu of not signing off at these timing corners. The timing analyst needs to decide what is appropriate depending upon the resources and schedule.

Also read:

• All about clock signals
• Is it possible for a logic gate to have negative delay
• Why depletion MOS cannot be used to create negative logic
• Propagation delay

Routing – connecting the dots within chip

Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.

VLSI routing is generally considered to be a complex combinatorial problem. Several algorithms have been developed for routing, each having its own pros and cons. The complexity of the routing problem is very high. To make it manageable, most routers usually take a two-step approach of global routing (approximation of routing wires) followed by detailed routing (actual routing of wires).

 

Global routing: Using a global routing algorithm, the router divides the design into tiles, each tile having a limited number of tracks and generates “loose” route for each connection by finding tile-to-tile paths (As shown in figure (ii)). The routes are not finalized, but the approximate length is known by the distance among the tiles. For example, a tile may have 12 tracks. So, global router will assign 12 tracks to each tile. But, the final assignment of the track is not done during global routing.

Detailed routing: Using detailed routing, the router determines the exact route for each net by searching within tile-to-tile path. It involves providing actual physical path to a net from one connected pin to another (as shown in figure (iii)). Hence, detailed routed wire represents actual resistance, capacitance and length of the net.

What router has to take care: While routing, a router has to pertain to specific constraints like timing budget for each critical net, also called performance constraints. There are other performance constraints too – like the router has to route in such a way as not to cause any crosstalk issues. There should not be any antenna issues. Also, there are a set of design rules like resistance, capacitance, wire/via width/spacing that need to be followed. For instance, technology may be limited by the minimum feature size it can have. Like, in 65 nm technology, the foundry cannot have wire widths less than 65 nm. So, the wires in the design have to be constrained to have wire length greater than 65 nm. Similarly, there are foundry specific constraints for other parameters. Each of these is termed as a Design Rule. Any violation pertaining to these in the design is termed as DRC (Design Rule Check) violation.

Grid based and gridless routing: In grid based routing, a routing grid is superimposed on routing region. Routing takes place along the grid lines. The space between adjacent grid lines is called wire pitch and is equal to sum of minimum width of wires and spacing of wires. On the other hand, any model that does not follow grid based routing is termed as gridless routing model. This model is suitable for wire sizing and perturbation and is more complex and slower than grid based routing. In other words, grid based routing is much easier and simpler in implementation.

We have discussed here routing in VLSI designs. Although many advanced tools are available for achieving the purpose, most of these compromise with the quality of results to save run-time. Almost all tools have the option of routing with more emphasis on meeting timing or congestion. With most of the tools, in present day multi-million gate designs, perfect DRC-free routing (without opens and shorts) is generally not obtained in first pass. You have to route incrementally a few times to achieve the same.

 

Also read:

• Engineering Change Order (ECO)
• Spare cells
• Problem: Clock gating checks at a complex gate
• Defining a clock signal in VHDL
• Noise margins