Duty cycle degradation

In the post, we discussed about duty cycle variation of the clock source. However, this is not the only pain in half cycle timing paths. Along clock path also, duty cycle of the clock can degrade. This can effect timing of half cycle paths adversely. We will discuss this in some detail; and also discuss how to tackle this. 

How is there degradation in duty cycle of clock: In addition to source duty cycle variation, there can be assymmetry in rise delay vs fall delay of clock elements. For instance, a buffer may have nominal rise (0 -> 1) delay of 50 ns whereas 48 ns for fall delay (1 -> 0). So, if a clock pulse passes through it, it will eat a portion of this clock pulse as shown in figure 1 below. For more clarity, we have exaggerated the scenario with a fall delay of 30 ns.

There are a lot of delay elements in clock distribution networks (also called clock tree network) inside the SoC. So, this problem is bound to happen there. Let us say, clock path has 20 buffers, each having a rise delay 10 ps greater than fall delay. So, the high pulse will get shortened when the clock reaches its sink. See how the pulse gets shortened if there is asymmetry in rise vs fall delay of a delay element or logic gate in below figure.

Even if we assume that the delay element has rise delay equal to fall delay, still, there is possibility of duty cycle degradation. Normally, a buffer (or inverter) has a nominal delay with some delay variations (for instance, OCVs) to be taken into account. For instance, it may have a rise delay of 100 ps with OCV variation to be taken of 5%. So, depending upon the scenario, we need to take its delay as either 95 ps or 105 ps. Similarly, even if we say that fall delay is exactly equal to rise delay, even then because of OCV variations, fall delay to be taken into account will be different than rise delay. Let us suppose, there are 20 such buffers in clock path with an ideal clock source. Then, we will have uncertainty in arrival of both rise and fall edges. And the effect will be visible in timing paths' slack.

How duty cycle degradation impacts timing: Degradation in duty cycle impacts timing wherever both rising and falling edges of clock are involved. For instance, it will impact half cycle timing paths as well as minimum pulse width check. You can go through our post duty cycle of clock to have an idea of the impact.

Also read:

• Interview questions related to clock jitter and duty cycle variations

Duty cycle variation of inter-clock timing paths

In the post, duty cycle variation, we understood what duty cycle variation is, and how to apply for intra-clock timing paths. But of similar importance is duty cycle variation as applied to inter-clock timing paths. Let us discuss these cases one-by-one:

Root clock to root-inverted clock: Inverted clock is same as root clock in frequency, with phase inverted. So, duty cycle variation needs to be applied for following cases:

• Root rise edge -> generated rise edge
• Root fall edge -> generated fall edge
• Generated rise edge -> Root rise edge
• Generated fall edge -> Root fall edge

Following commands will be needed to be applied:

set_clock_uncertainty -rise_from root_clk -rise_to gen_clk <duty_cycle> 

set_clock_uncertainty -fall_from root_clk -fall_to gen_clk <duty_cycle>

set_clock_uncertainty -rise_from gen_clk -rise_to root_clk <duty_cycle>

set_clock_uncertainty -fall_from gen_clk -fall_to root_clk <duty_cycle>

Root clock to odd 50% divided clock: In this scenario, we need to apply extra uncertainty for the following cases:

• Root rise edge -> Generated fall edge
• Root fall edge -> Generated rise edge
• Generated rise edge -> Root fall edge
• Generated fall edge -> Root rise edge

Following commands will need to be applied for this case:

set_clock_uncertainty -rise_from root_clk -fall_to gen_clk <duty cycle>

set_clock_uncertainty -fall_from root_clk -rise_to gen_clk <duty cycle>

set_clock_uncertainty -rise_from gen_clk -fall_to root_clk <duty cycle>

set_clock_uncertainty -fall_from gen_clk -rise_to root_clk <duty cycle>

Root clock to even 50% divided clock: In this case, we need to apply duty cycle uncertainty for the following cases:

• Root fall edge -> Generated rise edge
• Root fall edge -> Generated fall edge
• Generated rise edge -> Root fall edge
• Generated fall edge -> Root fall edge

Below figure shows these cases for a 50% divided clock from root clock.

So, the rule of thumb is same. Wherever there is a timing path wherein both rising and falling edges of root clock are involved, duty cycle variation will come into play. If you just keep this basic thing into mind, duty cycle variation will never haunt you. :-)

Also read:

• Interview questions related to clock jitter and duty cycle variations

Duty cycle variation

Duty cycle variation: Similar to jitter in clock period, there can be variations in duty cycle of the clock source due to uncertainty in the relative timings of positive and negative edges. Duty cycle variation is always measured with respect to corresponding positive and negative edges. In other words, we can also say that duty cycle variation is the uncertainty in arrival of negative edge, given that positive edge has arrived at certain fixed point of time. Let us take an example. If we are given a clock with a period of 10 ns with ideal 50% duty cycle. Also, we are given that it has the clock has a duty cycle variation of +-5%. So, if we say that we saw positive edge of clock at 100 ns, we can expect to see negative edge of clock at any time between 14.5 ns and 15.5 ns. The timing waveform in figure 2 illustrates this. 

Similarly, if we know with certainty, the point of arrival of negative edge, there will be uncertainty in the time of arrival of positive edge of the clock.

Applying duty cycle variation: There may be specific command in STA tools to specify duty cycle variation of a clock. If that is available, you just need to specify duty cycle variation of the master clock source. And all the above discussed cases will be taken care automatically by the tool. If not, it can be applied with the help of SDC command "set_clock_uncertainty". For instance, to apply duty cycle variation for a clock named "clk" of 0.5 ns, we can apply following commands:

set_clock_uncertainty -rise_from clk -fall_to clk 0.5 -setup

set_clock_uncertainty -fall_from clk -rise_to clk 0.5 -setup

set_clock_uncertainty -rise_from clk -fall_to clk 0.5 -hold

set_clock_uncertainty -fall_from clk -rise_to clk 0.5 -hold 

Note that there are two commands that need to be applied as there are two categories of half cycle paths, rise-fall and fall-rise. 

Timing implication of duty cycle variation: The same way as clock period jitter impacts setup slack of full cycle timing paths; duty cycle variation plays a role in half cycle timing paths. That is why, duty cycle variation is also referred as half cycle jitter. Keeping in mind that there are a lot of cases available with divided and undivided clocks, we will discuss below how to apply duty cycle variation while calculating timing slack. We need to keep in mind that, simlar to full cycle jitter, duty cycle variation is the property of a clock source. With reference to duty cycle variation, there can be following categories of clocks.

• Master clock
• Even divided clocks from master clock with 50% duty cycle
• Odd divided clocks from master clock with 50% duty cycle
• Even divided clocks from inverted master clock with 50% duty cycle
• Odd divided clocks from inverted master clock with 50% duty cycle
• Non-50% divided clocks/arbitrary divided clocks

Corresponding to these clock categories, there will be multiple cases, some or all of which may be present in your design. And depending upon the scenario, you may need to apply clock uncertainty for that particular case. A simple rule of thumb is that we should apply uncertainty for that scenario wherein the timing path involves both rise and fall edges of master clock. Let us discuss all these one by one:

Intra-clock timing paths:

Duty cycle variation of master clock: For a master clock, there will be a duty cycle variation as specified by the specifications of the clock source. So, if there are half cycle timing paths being formed with respect to this clock, we need to apply clock uncertainty for rise->fall and fall->rise timing paths as suggested by figure below.

So, the commands that need to be applied are:

set_clock_uncertainty <duty_cycle_variation> -rise_from clk -fall_to clk (both for setup and hold)

set_clock_uncertainty <duty_cycle_variation> -fall_from clk -rise_to clk (both for setup and hold)

where <duty_cycle_variation> is the duty cycle variation of clock source.

Duty cycle variation of odd divided clock: A divided clock with odd division factor with respect to root clock will have its positive edges aligned with respect to positive edge of root clock; and negative edges aligned to negative edges of root clock. Figure below illustrates this. So, if we assume that the positive edge is fixed (and neglecting clock period jitter), we can say that its negative edges have an uncertainty which is equal to that of root clock.

So, we need to apply following commands for duty cycle variations of odd_div_clock:

set_clock_uncertainty <duty_cycle_variation> -rise_from odd_div_clk -fall_to odd_div_clk

set_clock_uncertainty <duty_cycle_variation> -fall_from odd_div_clk -rise_to odd_div_clk

Duty cycle variation of even 50% divided clock: A divided clock with even division factor with respect to root clock will have both its positive and negative edges aligned to positive edge of root clock. Figure below illustrates this. So, for all the intra-clock paths being formed at this clock, duty cycle variation does not apply. This is one of the reasons why emphasis is given to always have even divided clocks in your design.

Duty cycle variation of arbitrary divided clocks: From the basics we have developed so far, duty cycle variation will be applied to a divided clock if its adjacent edges involve both rising and falling edges of the master clock (as in odd divided clocks) and will not be applied if it involves either only positive or only negative edges of root clock.

Figure below shows an example wherein divide-by-2 clock is generated through clock gating cell.  It has a duty cycle of 25%. Here, we need to apply duty cycle variation even as the clock is even divided.

Similarly, if an odd divided clock involves only positive or only negative edges of root clock, duty cycle variation will not apply. Figure below shows an example wherein there is a divide-by-3 clock with 33% duty cycle. Here, we dont need to apply duty cycle variation even though the clock is odd divided.

Also read:

• Interview questions related to clock jitter and duty cycle variations