Showing posts with label data invalid window. Show all posts
Showing posts with label data invalid window. Show all posts

Setup checks and hold checks for flop-to-flop paths

In the post (Setup time and hold time – static timing analysis), we introduced setup and hold timing requirements and also discussed why these requirements exist. In this post, we will be discussing how these checks are applied for different cases for paths starting from and ending at flip-flops.

In present day designs, most of the paths (more than 95%) start from and end at flip-flops (exceptions are there like paths starting from and/or ending at latches). There can be flops which are positive edge triggered or negative edge triggered. Thus, depending upon the type of launching flip-flop and capturing flip-flop, there can be 4 cases as discussed below:

1)      Setup and hold checks for paths launching from positive edge-triggered flip-flop and being captured at positive edge-triggered flip-flop (rise-to-rise checks): Figure 1 shows a path being launched from a positive edge-triggered flop and being captured on a positive edge-triggered flop. In this case, setup check is on the next rising edge and hold check is on the same edge corresponding to the clock edge on which launching flop is launching the data.

Positive edge-triggered flop to poritive edge-triggered flop path

Figure 1 : Timing path from positive edge flop to positive edge flop (rise to rise path)



Figure 2 below shows the setup and hold checks for positive edge-triggered register to positive edge-triggered register in the form of waveform. As is shown, setup check occurs at the next rising edge and hold check occurs at the same edge corresponding to the launch clock edge. For this case setup timing equation cab be given as:
            Tck->q + Tprop + Tsetup < Tperiod + Tskew               (for setup check)
And the equation for hold timing can be given as:
            Tck->q + Tprop > Thold + Tskew                                  (for hold check)
Where
        Tck->q  : Clock-to-output delay of launch register
        Tprop : Maximum delay of the combinational path between launch and capture register
       Thold : Hold time requirement of capturing register
       Tskew : skew between the two registers (Clock arrival at capture register - Clock arrival at launch register)
 



Also, we show below the data valid and invalid windows. From this figure,

                Data valid window = Clock period – Setup window – Hold window
                Start of data valid window = Tlaunch + Thold
                End of data valid window = Tlaunch + Tperiod – Tsetup

In other words, data at the input of capture register can toggle any time between (Tlaunch + Thold) and (Tlaunch + Tperiod – Tsetup).

Data valid window for positive edge-trigger flop to positive edge-triggered flop path is equal to clock period minus sum of setup window and hold window requirements

Figure 3: Figure showing data valid window for rise-to-rise path

2)        Setup and hold checks for paths launching from positive edge-triggered flip-flop and being captured at negative edge-triggered flip-flop: In this case, both setup and hold check are half cycle checks; setup being checked on the next falling edge at the capture flop and hold on the previous falling edge of clock at the capture flop (data is launched at rising edge). Thus, with respect to (case 1) above, setup check has become tight and hold check has relaxed.


A timing path startgin from positive edge-triggered flop and ending at negative edge-triggered flop

Figure 4: Timing path from positive edge flop to negative edge flop (Rise-to-fall path)

Figure 5 below shows the setup and hold checks in the form of waveforms. As is shown, setup check occurs at the next falling edge and hold check occurs at the previous falling edge corresponding to the launch clock edge. The equation for setup check can be written, in this case, as:
            Tck->q + Tprop + Tsetup  < (Tperiod/2) + Tskew                       (for setup check)
And the equation for hold check can be written as:
            Tck->q + Tprop + (Tperiod/2) > Thold + Tskew                         (for hold check)
 

In case of path from positive edge-triggered flop to negative edge-triggered flop, setup check is on the next negative edge and hold check is on the previous falling edge corresponding to the edge at which data is launched (positive edge of the clock)

Figure 5: Setup and hold checks for rise-to-fall paths

Also, we show below the data valid and invalid windows. From this figure, 

                Data valid window = Clock period – Setup window – Hold window
                Start of data valid window = Tlaunch – (Tperiod/2)+ Thold
                End of data valid window = Tlaunch + (Tperiod/2) – Tsetup

As we can see, the data valid window is spread evenly on both sides of launch clock edge.

 
Data valid window in case of positive edge-triggered flop to negative edge-triggered flop path extends between the two negative edges, with setup and hold margins reduced from the corresponding sides

Figure 6: Figure showing data valid window for rise-to-fall path

3)           Setup and hold checks for paths launching from negative edge-triggered flip-flop and being captured at positive edge-triggered flip-flop (rise-to-fall paths): This case is similar to case 2; i.e. both setup and hold checks are half cycle checks. Data is launched on negative edge of the clock, setup is checked on the next rising edge and hold on previous rising edge of the clock.

Figure to show a timing path from a negative edge-triggered flip-flop to a positive edge-triggered flip-flop

Figure 7: Timing path from negative edge flop to positive edge flop (fall-to-rise path)

Figure 8 below shows the setup and hold checks in the form of waveforms. As is shown, setup check occurs at the next rising edge and hold check occurs at the previous rising edge corresponding to the launch clock edge.  The equation for setup check can be written, in this case, as:

            Tck->q + Tprop + Tsetup  < (Tperiod/2) + Tskew                       (for setup check)

And the equation for hold check can be written as:
            Tck->q + Tprop + (Tperiod/2) > Thold + Tskew                         (for hold check)

In case of timing path from negative edge-triggered flip-flop to positive edge-triggered flip-flop, data launches at the negative edge of the clock. The setup check is on the next positive edge and hold check is on the previous rising edge corresponding to the launching edge.

Figure 8: Setup and hold checks for fall to rise paths

Also, we show below the data valid and invalid windows. From this figure,

                Data valid window = Clock period – Setup window – Hold window
                Start of data valid window = Tlaunch – (Tperiod/2)+ Thold
                End of data valid window = Tlaunch + (Tperiod/2) – Tsetup

In this case too, data valid window spreads evenly on both the sides of launch clock edge.
 
Data valid window extends from the previous positive edge to next positive edge corresponding to launch edge, with setup and hold margind reduced from corresponding sides.

Figure 9: Figure showing data valid window for fall-to-rise path


4)             Setup and hold checks for paths launching from negative edge-triggered flip-flop and being captured at negative edge-triggered flip-flop (fall-to-fall paths): The interpretation of this case is similar to case 1. Both launch and capture of data happen at negative edge of the clock. Figure 10 shows a path being launched from a negative edge-triggered flop and being captured on a negative edge-triggered flop. In this case, setup check is on the next falling edge and hold check is on the same edge corresponding to the clock edge on which launching flop is launching the data.

Figure to show a timing path being launched from negatice edg of the clock and being captured at the negative edge of the clock

Figure 10: Path from negative edge flop to negative edge flop (fall to fall path)

Figure below shows the setup and hold checks in the form of waveforms. As is shown, setup check occurs at the next falling edge and hold check occurs at the same edge corresponding to the launch clock edge. 
The equation for setup check can be given as:
                Tck->q + Tprop + Tsetup < Tperiod + Tskew                (for setup check)
And the equation for hold check can be given as:
               Tck->q + Tprop > Thold + Tskew                                                    (for hold check) 


In case of paths starting from negative edge-triggered flop and ending at negative edge-triggered flop, data is launched from negative edge. Setup check is on the next negative edge and hold check is on the same edge corresponding to the launch clock edge

Figure 11: Setup and hold check for fall-to-fall path


Also, we show below the data valid and invalid windows. From this figure,

                Data valid window = Clock period – Setup window – Hold window
                Start of data valid window = Tlaunch + Thold
                End of data valid window = Tlaunch + Tperiod – Tsetup


 
Data valid window ranges between the two negative edges, with setup or hold margin reduced from each side

Figure 12: Figure showing data valid window for fall-to-fall path