Clock multiplexer for glitch-free clock switching

In the post clock switching and clock gating checks, we discussed how important it is to have a glitch free clock. Also, in clock gating checks at a multiplexer, we discussed the conditions wherein a normal multiplexer can be used to propagate a clock without any glitches. 

In this post, we will discuss about multiplexer circuit for clock switching which can safely switch clocks without the probability of any glitches under most of the scenarios, hence, also called glitch-less multiplexer.

Definition of clock multiplexer: Let us first define a clock multiplexer "A clock multiplexer is a circuit that can switch the system from one clock to another while the chip is running. The two frequencies may be related to each other, or may to totally unrelated". A clock multiplexer switches the clock without any glitches as the glitch in clock will be hazardous for the system. Hence, a clock multiplexer is also known as a glitchless multiplexer.

Clock multiplexer for switching between two synchronous clocks:

Clock multiplexer for switching between two asynchronous clocks:

Reference: A very detailed and good explanation is provided at below link. I recommend to go through this for complete understanding of the process.
http://www.eetimes.com/document.asp?doc_id=1202359

Also read:

• Clock gating interview questions

STA problem: Finding setup and hold slack taking into accoung clock skew

Problem: Figure 1 below shows a timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop. Considering clock frequency of 200 MHz, find the setup and hold slacks for this timing path.

Solution:

Figure 1: Timing path

As the clock frequency is given as a 200 MHz, time period = 1/frequency = 5 ns.

Let us first calculate the setup slack. The setup timing equation is given as:

T_ck->q + T_prop + T_setup - Tskew < T_period

And equation for setup slack is given as:

SS = T_{period -} (T_ck->q + T_prop + T_setup - Tskew₎  

Here,

T_ck->q = 2ns, T_prop (max value of delay of combinational logic) = 4 ns+ T_setup = 1 ns,   T_period = 5 ns, Tskew = 1 ns

 Putting these values into equation for setup slack, we get setup slack for this timing path.

SS = 5 - (2 + 4 + 1 - 1) ns

SS = -1 ns

Now, hold slack can be found out from the hold timing equation. The hold timing equation is given as:

T_ck->q  + T_prop > T_hold + T_skew

Here,

T_ck->q  =  2 ns, T_prop (min value of combinational propagation delay) = 4 ns, T_hold = 1ns, T_skew = 1 ns

 And the equation for hold slack is given as:

HS = T_ck->q  + T_prop  - (T_hold + T_skew) 

HS = 2 + 4 - (1 + 1) = 4 ns 

So, for this timing path, setup slack value is -1 ns and hold slack value is 4 ns.