Clock gating interview questions

One of the most important and frequently asked topics in interviews is clock gating and clock gating checks. We have a collection of blog-posts related to this topic which can help you master clock gating. You can go through following links to add to your existing knowledge of clock gating:

• Clock gating - basics: Discusses the basic concept and principle of clock gating

• How clock gating saves dynamic power: Discusses how dynamic power is saved with clock gating

• Need for clock gating checks: Discusses why clock gating checks are needed for glitchless propagation of clock

• Clock gating checks: Discusses different clock gating structures used and associated timing checks related to these

• Clock gating checks at a mux: Discusses clock gating checks that should be applied in case one of the inputs of mux has a clock signal connected to it, which is the most common clock gating check in today's designs

• Quiz: Clock gating checks at a complex gate: Discusses how to proceed if there is a random combinational cell having a clock at one of its inputs

• Integrated clock gating cell: Discusses the special clock gating cell used in designs to implement clock gating in today's designs

• Can we use discrete latches and AND/OR gates instead of ICG? : Discusses the advantages of using integrated clock gating cell, instead of discrete AND/OR gates and latches.

• Clock multiplexer for glitch-free clock switching: Discusses the structure of glitchless mux. 

• Design problem: Clock gating for a shift register: Discusses how we can clock gate a complete module with the help of a simple example.

• Clock gating checks in case of mux select transition when both clocks are running: A design example showing complex application of clock gating checks

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