Problem: Figure 1 below shows a timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop. Considering clock frequency of 200 MHz, find the setup and hold slacks for this timing path.
Figure 1: Timing path |
As the clock frequency is given as a 200 MHz, time period = 1/frequency = 5 ns.
Let us first calculate the setup slack. The setup timing equation is given as:
Tck->q + Tprop + Tsetup - Tskew < TperiodAnd equation for setup slack is given as:
SS = Tperiod - (Tck->q + Tprop + Tsetup - Tskew)Here,
Tck->q = 2ns, Tprop (max value of delay of combinational logic) = 4 ns+ Tsetup = 1 ns, Tperiod = 5 ns, Tskew = 1 nsPutting these values into equation for setup slack, we get setup slack for this timing path.
SS = 5 - (2 + 4 + 1 - 1) ns
SS = -1 ns
Now, hold slack can be found out from the hold timing equation. The hold timing equation is given as:
Here,Tck->q + Tprop > Thold + Tskew
Tck->q = 2 ns, Tprop (min value of combinational propagation delay) = 4 ns, Thold = 1ns, Tskew = 1 nsAnd the equation for hold slack is given as:
HS = Tck->q + Tprop - (Thold + Tskew)
HS = 2 + 4 - (1 + 1) = 4 nsSo, for this timing path, setup slack value is -1 ns and hold slack value is 4 ns.
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