2x1 mux using NAND gates

As we know, the logical equation of a 2-input mux is given as below:

                      Y = (s' A   +    s B)

Where s is the select of the multiplexer.
De-Morgan's law states that
                                m + n = (m'n')'

Taking this into account, here m = s'A  and  n = sB

                     Y = ((s'A)'(sB)')' = ((s' A)'  (s B)')'

Thus, Y is equal to ((s' nand A) nand (s nand B)). No further optimizations seem possible to this logic. Figure 1 below shows the implementation of 2:1 mux using 2-input NAND gates.

Figure 1: 2:1 Mux using NAND gates

3-input AND gate using 4:1 mux

As we know, a AND gate's output goes '1' when all its inputs are '1', otherwise it is '0'. The truth table for a 3-input AND gate is shown below in figure 1, where A, B and C are the three inputs and O is the output.

                                      O = A (and) B (and) C

Truth table for 3-input AND gate

A 4:1 mux has 2 select lines. We can connect A and B to each of the select lines. The output will, then, be a function of the third input C. Now, if we sub-partition the truth table for distinct values of A and B, we observe

When A = 0 and B = 0, O = 0 => Connect D0 pin of mux to '0'

When A = 0 and B = 1, O = 0 => Connect D1 pin of mux to '0'

When A = 1 and B = 0, O = 0 => Connect D2 pin of mux to '0'

When A = 1 and B = 1, O = C => Connect D3 pin of mux to C

The implementation of 3-input AND gate, based upon our discussion so far, is as shown in figure 2 below:

Also read:

• XOR gate implementation using NAND gates
• 16x1 mux using 4x1 muxes
• 2-inputs gates using 2:1 mux
• 3-input AND gate using 2:1 muxes