Bubble errors and bubble error correction

Bubble error correction is a very common term associated to flash ADCs (see flash ADC block diagram) wherein the output produced by comparators stage is expected to be a thermometer code. However, due to multiple non-idealities and mismatches in comparators and their inputs, the output may not be a symbol of thermometer code, but has some irregularities. So, the thermometer to binary converter stage may not be able to convert it to binary code as it is generally a state machine that accepts only thermometer code as input and may produce a garbage output if provided some other input that is not thermometer code. There may be some zeroes in-between a series of ones. For example, the output may be “01011111” instead of “01111111”. “01011111”, when fed to thermometer to binary converter will produce garbage value. Either “01111111” should be given or “00111111” or “00011111”. This will reduce the error. The presence of zeroes in a series of ones or presence of ones in a series of zeroes in the comparators’ output is termed as bubble error. And the removal of these bubbles from near-thermometer code is termed as bubble error correction.

Kinds of bubble errors: Bubble errors are categorized by their order. A first order bubble error means there is only single ‘1’ between a series of zeroes or vice-versa. For example, “0010001101” has two first order bubbler, on second bit from right and third bit from left. Similarly, “01100001111” has a second order bubble. “00011100000000010111” has one third-order and one first-order bubble.

What circuit can be used to correct bubble errors? The simplest circuit that can be used to correct bubble errors is majority-of-three circuit. In it, each output is compared with one output on the left and one on the right. The majority of the three is finally produced at the output. This is how a near-thermometer code will be converted to a thermometer code. However, a majority of three circuit will be able to correct bubble errors of first order only. There are more sophisticated circuits for second and higher order bubble correction.

            Hope you’ve found this post useful. Let us know what you think in the comments.

Delay line based Time to digital converter

A time to digital converter is a circuit that digitizes time; i.e., it converts time into digital number. In other words, a time-to-digital converter measures the time interval between two events and represents that interval in the form of a digital number.

TDCs are used in places where the time interval between two events needs to be determined. These two events may, for example, be represented by rising edges of two signals. Some applications of TDCs include time-of-flight measurement circuits and All-Digital PLLs.

Delay line based time-to-digital converter: This is a very primitive TDC and involves a delay-line which is used to delay the reference signal. The other signal is used to sample the state of delay chain. Each stage of delay chain outputs to a flip-flop or a latch which is clocked by the sample signal. Thus, the output of the TDC forms a thermometer code as the stage will show a ‘1’ if the reference signal has passed it, otherwise it will show a zero. The schematic diagram of delay line based time-to-digital converter is shown in figure 1 below:

Figure 1: Delay line based Time-to-digital converter

The VHDL code for delay line based time-to-digital converter is given below:

-- This is the module definition of delay line based time to digital converter.

library ieee;

use ieee.std_logic_1164.all;        

entity tdc is

                generic (

                                number_of_bits : integer := 64

                );

                port (

                                retimed_clk : in std_logic;

                                variable_clk : in std_logic;

                                tdc_out : out std_logic_vector (number_of_bits-1 downto 0);

                                reset : in std_logic

                );

end entity;

architecture behavior of tdc is

                component buffd4 is port (

                                I : in std_logic;

                                Z : out std_logic

                );

                end component;

                signal buf_inst_out : std_logic_vector (number_of_bits downto 0);

begin

--buffd4

                buf_inst_out(0) <= variable_clk;

                tdc_loop : for i in 1 to (number_of_bits) generate

                begin

                                buf_inst : buffd4 port map (

                                                I => buf_inst_out(i-1),

                                                Z => buf_inst_out(i)

                                );

                end generate;

                process (reset,retimed_clk)

                begin

                                if reset = '1' then

                                                tdc_out <= (others => '0');

                                elsif retimed_clk'event and retimed_clk = '1' then

                                                tdc_out <= buf_inst_out(number_of_bits downto 1);

                                end if;

                end process;

end architecture;

References:

• Time-to-digital converter basics - Springer

Hope you’ve found this post useful. Let us know what you think in the comments.

Interesting problem – Latches in series

Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?

Figure 1 : 100 negative level-sensitive latches in series

As we know, setup check between latches of same polarity (both positive or negative) is zero cycle with half cycle of time borrow allowed as shown in figure 2 below for negative level-sensitive latches:

Figure 2: Setup check between two negative level-sensitive latches

So, if there are a number of same polarity latches, all will form zero cycle setup check with the next latch; resulting in overall zero cycle phase shift.

As is shown in figure 3, all the latches in series are borrowing time, but allowing any actual phase shift to happen. If we have a design with all latches, there cannot be a next state calculation if all the latches are either positive level-sensitive or negative level-sensitive. In other words, for state-machine implementation, there should not be latches of same polarity in series.

Figure 3 : Timing for 100 latches in series

Hope you’ve found this post useful. Let us know what you think in the comments.

Also read:

• Build a latch using a 2:1 multiplexer
• Multicycle paths handling in STA
• Latchup in CMOS devices
• Lockup latch - principle, application and timing
• Data checks - all about data setup and data hold checks

XOR/XNOR gate using 2:1 MUX

2-input XOR gate using a 2:1 multiplexer: As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select input. The function of a 2:1 multiplexer can be given as:

OUT = IN0 when SEL = 0 ELSE IN1

Also, a 2-input XOR gate produces a ‘1’ at the output if both the inputs have different value; and ‘0’ if the inputs are same. The truth table of an XOR gate is given as:

A	B	OUT
0	0	0
0	1	1
1	0	1
1	1	0

Truth table of XOR gate

In the truth table of XOR gate, if we fix a value, say B, then

OUT = A WHEN B = 0 ELSE A’

Both the above equations seem equivalent if we connect negative of IN0 to IN1 in a multiplexer. This is how a 2:1 multiplexer will implement an XOR gate. Figure 1 below shows the implement of a 2-input XOR gate using a 2:1 Multiplexer.

Implementing a 2-input XOR gate using a 2:1 Multiplexer

I hope you’ve found this post useful. Let me know what you think in the comments. I’d love to hear from you all.

2-input XNOR gate using a 2:1 multiplexer: Similarly, the truth table of XNOR gate can be written as:

A	B	OUT
0	0	1
0	1	0
1	0	0
1	1	1

Truth table of XNOR gate

In the truth table, if we fix, say A, then

OUT = B WHEN A = 1, ELSE B’

Thus, XNOR gate is the complement of XOR gate. It can be implemented if we connect A to IN1 and Abar to IN0.

2-input XNOR gate using 2:1 multiplexer

Read also:

• Build a latch using 2:1 multiplexer
• Clock gating checks at a multiplexer
• Implementing 3 and 4 variable functions using a multiplexer
• Interesting Design problem - BCD multiply by 5 circuit

How propagation of ‘X’ happens through different logic gates

‘X’ refers to a signal attaining a value that is ‘unknown’. It can be either ‘0’ or ‘1’. But, the exact value of the signal is not known. If a simulator is not able to decide whether a logic value should be logic ‘0’ or logic ‘1’, it will assign a value ‘X’ to the value. An example of ‘X’ source is a logic block that has not been initialized properly through reset. Having an ‘X’ value at a node can propagate to the logic lying in the fan-out, thereby increasing the uncertainty downstream the logic.

How ‘X’ propagates: An ‘X’ value at the input of a logic gate may or may not propagate to its output depending upon the states at other inputs of the logic gate. Given below is how different logic gates react to ‘X’ values:

1)  OR gate: An OR gate can absorb an ‘X’ if the other input has logic ‘1’. Otherwise, ‘X’ propagates through it. Please refer figure 1 for explanation:

Figure 1: X-propagation through OR gate

2) AND gate: An AND gate can absorb ‘X’ if the other input has logic ‘0’. Otherwise, ‘X’ propagates through it. Please refer figure 2 for explanation:

Figure 2: X-propagation through AND gate

3) Buffer/inverter: Since, buffers/inverters are single input gates, an ‘X’ at the input means ‘X’ at the output.

4) XOR gate: An ‘X’ at one of the inputs of XOR produces ‘X’ at the output no matter what the 

other input state is. Please refer truth table given in Figure 3 for explanation:

Figure 3: X-propagation through XOR gate

5) Complex gates: For complex gates, whether ‘X’ will propagate to the output depends upon the overall function of the ‘X’ input with respect to other gates. E.g. suppose a gate with function

Z = A + (B * C)

Then, if B input goes ‘X’, the output will go ‘X’ if A=0 and C=1.

Read also:

• Carry Look Ahead Adder
• MBIST (Memory Built-In Self Test)
• Controllability and observability - two DFT principles
• Digital counters
• Regions of operation of MOS transistors

Can a net have negative propagation delay?

As we discussed in ‘’Is it possible for a logic gate to have negative propagation delay”, a logic cell can have negative propagation delay. However, the only condition we mentioned was that the transition at the output pin should be improved drastically so that 50% level at output is reached before 50% level of input waveform.

In other words, the only condition for negative delay is to have improvement in slew. As we know, a net has only passive parasitic in the form of parasitic resistances and capacitances. Passive elements can only degrade the transition as they cannot provide energy (assuming no crosstalk); rather can only dissipate it. In other words, it is not possible for a net to have negative propagation delay.

However, we can have negative delay for a net, if there is crosstalk, as crosstalk can improve the transition on a net. In other words, in the presence of crosstalk, we can have 50% level at output reached before 50% level at input; hence, negative propagation delay of a net.

Also read:

• Bubble errors and bubble error correction
• Noise margins
• Can hold be frequency dependant
• Worst slew propagation
• Latchup in CMOS devices

Can hold check be frequency dependant?

We often encounter people argue that hold check is frequency independent. However, it is only partially true. This condition is true only for zero-cycle hold checks. By zero cycle hold checks, we mean that the hold check is performed on the same edge at which it is launched. This is true in case of timing paths between same polarity registers; e.g. between positive edge-triggered flops. Figure 1 below shows timing checks for a data-path launched from a positive edge-triggered flip-flop and captured at a positive edge-triggered flip-flop. The hold timing, in this case, is checked at the same edge at which data is launched. Changing the clock frequency will not cause hold check to change.

Figure 1: Setup and hold checks for positive edge-triggered to positive edge-triggered flip-flop

Most of the cases in today’s designs are of this type only. The exceptions to zero cycle hold check are not too many. There are hold checks for previous edge also. However, these are very relaxed as compared to zero cycle hold check. Hence, are not mentioned. Also, hold checks on next edge are impossible to be met considering cross-corner delay variations. So, seldom do we hear that hold check is frequency dependant. Let us talk of different scenarios of frequency dependant hold checks:

1.  From positive edge-triggered flip-flop to negative edge-triggered flip-flop and vice-versa: Figure 2 below shows the setup and hold checks for a timing path from positive edge-triggered flip-flop to a negative edge-triggered flip-flop. Change in frequency will change the distance between the two adjacent edges; hence, hold check will change. The equation for hold timing will be given for below case as:

T_data + T_clk/2 > T_skew + T_hold

or

Tslack =  T_clk/2 - T_hold - T_skew + T_data

          Thus, clock period comes into picture in calculation of hold timing slack.

Figure 2: Setup and hold checks for timing path from positive edge-triggered flip-flop to negative edge-triggered flip-flop

Similarly, for timing paths launching from negative edge-triggered flip-flop and being captured at positive edge-triggered flip-flop, clock period comes into picture. However, this check is very relaxed most of the times. It is evident from above equation that for hold slack to be negative, the skew between launch and capture clocks should be greater than half clock cycle which is very rare scenario to occur. Even at 2 GHz frequency (T_clk = 500 ps), skew has to be greater than 250 ps which is still very rare.

Coming to latches, hold check from a positive level-sensitive latch to negative edge-triggered flip-flop is half cycle. Similarly, hold check from a negative level-sensitive latch to positive edge-triggered flip-flop is half cycle. Hence, hold check in both of these cases is frequency dependant.

2. Clock gating hold checks: When data launched from a negative edge-triggered flip-flop gates a clock on an OR gate, hold is checked on next positive edge to the edge at which data is launched as shown in figure 3, which is frequency dependant.

Figure 3: Clock gating hold check between data launched from a negative edge-triggered flip-flop and and clock at an OR gate

           Similarly, data launched from positive edge-triggered and gating clock on an AND gate form half cycle hold. However, this kind of check is not possible to meet under normal scenarios considering cross-corner variations.

3)      Non-default hold checks: Sometimes, due to architectural requirements (e.g. multi-cycle paths for hold), hold check is non-zero cycle even for positive edge-triggered to positive edge-triggered paths as shown in figure 4 below.

Figure 4: Non-default hold check with multi-cycle path of 1 cycle specified

Also read:

• Lockup latch - principle, application and timing
• Data checks - all about data setup and data hold checks
• Worst slew propagation
• On-chip variations - the STA takeaway

Latency and throughput – the two measures of system performance

Performance of the system is one of the most stringent criteria for its success. While performance increases the desirability among customers, cost is what makes it affordable. This is the reason why system designers aim for maximum performance with available resources such as power and area constraints. There are two related parameters that determine the performance output of a system –

Throughput - Throughput is a measure of the productivity of the system. In electronic/communication systems, throughput refers to rate at which output data is produced. Higher the throughput, more productive is the system. In most of the cases, it is measured as time difference between two consecutive outputs (nth and n+1th). Throughput also refers to the rate at which input data can be applied to system.

Let us discuss with the help of an example:

Above figure depicts the throughput of 3 number adder. Result of input set applied at 1st clock cycle appears at output at 3rd clock cycle and in 4th clock cycle next input set is applied and output comes in 6th clock cycle.  Hence, throughput of above design is ⅓ per clock cycle. As we can see from diagram, first input is applied in first clock cycle and 2nd input is applied in 4th clock cycle. Hence we can also say that throughput is rate at which input data can be applied to system.

Latency- Latency is the time taken by a system to produce output after input is applied. It is a measure of delay response of a design. Higher the latency value, slower is the system. in synchronous designs, it is measured in terms of number of clock cycles. In combinational designs, latency is basically propagation delay of circuit. In non pipelined designs, latency improvement is major area of concern. In more general terms, it is time difference between output and input time.

Relationship between throughput and latency: Both latency and throughput are inter-related. It is desired to have maximum throughput and minimum latency. Increasing latency and/or throughput might make the system costly. Let us take an example. Consider a park with 3 rides and it takes 5 minutes for a ride.  A child can take sequentially these rides; i.e, ride 1, ride 2 and then ride 3. Firstly, let us assume that only one child at a time is allowed to enter park at a time. While he is taking a ride, no one is allowed to enter the park. Thus, the throughput of the park is 15 minutes per child and latency is 15 minutes. Now, let us assume that while a child has finished taking ride1, another child is allowed to enter park. Thus, in this case, throughput will be 5 minutes per child whereas latency is still 15 minutes. Thus, we have increased the throughput of the system without affecting latency and at the same cost.

What is Logic Built-in Self Test (LBIST)

LBIST stands for Logic Built-In Self Test. As VLSI marches to deep sub-micron technologies, LBIST is gaining importance due to the unique advantages it provides. LBIST refers to a self-test mechanism for testing random logic. The logic can be tested with no intervention from the outside world. In other words, a piece of hardware and/or software is inbuilt into an integrated circuit to test itself. By random logic, is meant any form of hardware (logic gates, memories etc.) that can form a part or whole of the chip. A generic LBIST system is implemented using STUMPS (Self-Test Using MISR and PRPG) architecture. A typical LBIST system is as shown in the figure below:

Figure 1: A typical LBIST system

Components of an LBIST system: A typical LBIST system comprises following:

1. Logic to be tested, or, as is called Circuit Under Test (CUT): In case of LBIST, the logic to be tested through LBIST is the Circuit under Test (CUT). Any random logic residing on the chip can be brought under LBIST following a certain procedure.
2. PRPG (Pseudo-Random Pattern Generator): A PRPG generates input patterns that are applied to internal scan chains of the CUT for LBIST testing. In other words, PRPG acts as a Test Pattern Generator (TPG) for LBIST. A PRPG can either use a counter or an LFSR for pattern generation.
3. MISR (Multi-Input Signature Register): MISR obtains the response of the device to the test patterns applied. An incorrect MISR output indicates a defect in the CUT. In classical language, MISR acts as a ORA (Output Response Analyzer) for LBIST testing.
4. A master (LBIST controller): The controller controls the functioning of the LBIST; i.e. clocks propagation, initialization and scan patterns flow in and out of the LBIST scan chains.

One of the most stringent requirements in LBIST testing is the prohibition of X-sources. There cannot be any source of ‘X’ during LBIST testing. By ‘X’, is meant a definite, but unknown value. It might be either ‘0’ or ‘1’, but it is not known what value is being propagated. All X-sources are masked and a known value is allowed to be propagated in LBIST.

Why ‘X’ is prohibited in LBIST: As stated above, there cannot be any ‘X’ propagating during LBIST testing. The reason behind this is that LBIST involves MISR to calculate the signature of the LBIST patterns. Since, the resulting signal is unique, any unknown value can result in the corruption of the signature. So, there cannot be any ‘X’ in LBIST testing.

Advantages of LBIST: As stated above, there are many unique advantages of LBIST that make it desirable, especially in safety critical designs such as those used in automobiles and aeroplanes. LBIST offers many advantages as listed below:

• LBIST provides self-test capability to logic inside chip; thus, the chip can test itself without any external control and interference.
• This provides the ability to be tested at higher frequencies reducing test time considerably.
• LBIST can run while the chip is on field running functionally. Thus, it is very useful in safety critical applications wherein faults developed on field can be easily detectable at startup before chip goes into functional mode.

Overheads due to LBIST: Along with many advantages, there are some overheads due to LBIST as mentioned below:

(i)                  The LBIST implementation involves some hardware on-chip to control LBIST. So, there are area and power impacts due to these. In other words, the cost of chip increases.

(ii)                Also, ‘X’-masking involves addition of extra logic gates in already timing critical functional signals causing impact on timing as well.

(iii)               Another disadvantage of using LBIST is that even the on-chip test equipment may fail. This is not the problem with testing using outside equipment with proven test circuitry

References:

1. Identification and reduction of safe-stating points in LBIST designs 
2. Logic built-in self-test
3. Challenges in LBIST verification of high reliability SoCs

Also read:

• MBIST (Memory Built-In Self Test)
• Lockup latch - principle, application and timing
• Controllability and observability - basics of DFT
• X-propagation through different logic gates
• Meyer's singleton pattern

Depletion MOSFET and negative logic. Why it is not possible?

As we know, depletion MOSFET conducts current even with gate and source at same voltage level. To cut-off the current in depletion MOSFET, a voltage has to be applied at gate so as to exhaust the already existing carriers inside the channel. On the other hand, enhancement type MOSFET is cut-off when gate and source are at same voltage.

Taking the example of NMOS, for a depletion MOS, with source and gate at same level, there is still a channel available, hence, it conducts electric current. To bring it to cut-off, a negative potential is needed to be applied at gate (considering source at ‘X’ potential). Thus, with source at ‘X’ potential and gate at ‘X’ potential, drain attains the potential of source. Since, to cut-off the device, gate has to be given a voltage less than ‘X’, so we can say “when Gate is 1 and source is 1, then drain is 1”.  On the other hand, when source is 1 and gate is 0, drain attains ‘high impedance’. The reverse is true for PMOS.

Similarly, with the same logic, for an enhancement NMOS, “When Gate is 1 and source is 0, drain attains 0 potential”; similarly, “When Gate is 0 and source is 0, drain is 0”. The reverse is true for PMOS.

Source voltage	Gate voltage	Drain voltage for enhancement NMOS	Drain voltage for enhancement PMOS	Drain voltage for depletion NMOS	Drain voltage for depletion PMOS
0	0	Z	Z	0	0
0	1	0	Z	0	Z
1	0	Z	1	Z	1
1	1	Z	Z	1	1

Thus, we can say that it is due to the inherent properties of NMOS and PMOS that that they cannot be used to create negative level logic.