Metal ECO - the process

A metal-only ECO is carried out by changing only metal interconnects in the design. Metal-only ECOs are very common in today’s semiconductor industry as they save complete silicon re-spin. Sometimes there may be need to change the design for various reasons, and that too, a minor change. These changes may be due to some bug in the design or due to customer demand. A metal-only ECO enables the design to be re-fabricated only for a few layers. It is very cost-effective as for complete silicon re-spin, there may be a requirement of around 100 layer masks to be manufactured. Metal-only ECOs enable the older masks to be used for most of the layers. Only the layers with changes in them need to be manufactured again, which is usually 2 to 4 in case of metal-only ECOs.

The steps to carry out metal-only ECOs are explained below:

1.) A number of spare cells are sprinkled throughout the design before being taped-out so as to facilitate metal layer ECOs later on. The set of spare cells is chosen very carefully considering in mind the nature of design and the probability of metal ECO later on (it depends upon how mature the design building blocks are)

2.)  First, the changes to be made are evaluated if these can be carried out by changing only metal layers. For this purpose, spare cells in the vicinity of the ECO location need to be observed. If there is enough number of spare cells there, these can be used. On the other hand, if there is not enough number of spare cells to represent the logic change, the ECO cannot be carried out using only metal layers. It has to be, then, carried out using all the layers as more cells will need to be added. It will, then, result in re-spin of the design. 

3.) If there is enough number of spare cells available, the appropriate spare cells to represent the design change are selected in the vicinity of the logic to be changed. Interconnects are, then, modified so as to represent the modified circuit. 

4.) The resulting layout is checked for timing and DRC/LVS violations. If everything is fine, the design is sent to be fabricated. There, masks for the modified layers are manufactured using the older masks for layers not modified.

5.) If there is any violation related to timing or DRC/LVS, steps 2, 3 and 4 are repeated until the design is clean with respect to these.

Also read:

• Engineering Change Order (ECO)
• Routing - connecting the dots withing chip
• Setup time and hold time - static timing analysis
• Timing corners - dimensions in timing signoff
• Can a net have negative propagation delay

References –

·         http://www.cadence.com/Community/blogs/ii/archive/2010/11/23/user-interview-how-metal-only-ecos-save-full-silicon-respins.aspx

Digital Counters

Digital Counters, as the name suggests, are digital circuits used for counting occurrence of any event. For any digital system like a computer, counters are most useful and versatile subsystem. A flip-flop can be used as a counter to count two states since Flip flop has two states either 0 or 1. Similarly, two flip-flops can be connected together to count 4 states (00, 01, 10, 11). Thus, with n flip-flops, we can make a counter that can count maximum 2ⁿ stages . Digital counters have following properties:

1)      Asynchronous or Synchronous – Asynchronous counters are one in which output of one flip-flop drives succeeding FF. Only first FF needs clock. All other Flops will be driven by its preceding FF. While in synchronous counters All FF are clocked by same external clock pulse.    

2)      Maximum number of counts – Also known as Modulus of counter. Modulus of counter is equal to total number of distinct stages through which counter progresses. For example:  A 4 Flip flop counter is often referred to as mod-16 counter i.e it can count 16 stages.

3)      Up or down counter – It dictates whether counter counts in upward or downward direction. For exp . 0 ->1->2->3->4->5->6->7 is up counter. 7->6->5->4->3->2->1->0 is down counter. The counter which can count in up or down direction depending upon some external signal(e.g.  if up(some external signal) is 1, count in upward direction else in downward) is called up-down counter.

4)      Free running or self stopping – if counter begins counting again after reaching its maximum stage,counter is called free running and if it stops after reaching maximum stage value it is called self stopping. Free running counters are also known as blind running counters.

Help improve this post!!

All about clock signals

Today’s designs are dominated by digital devices. These are all synchronous state machines consisting of flip-flops. The transition from one state to next is synchronous and is governed by a signal known as clock. That is why, we have aptly termed clock as ‘the in-charge of synchronous designs’. 

Definition of clock signal: We can define a clock signal as the one which synchronizes the state transitions by keeping all the registers/state elements in synchronization. In common terminology, a clock signal is a signal that is used to trigger sequential devices (flip-flops in general). By this, we mean that ‘on the active state/edge of clock, data at input of flip-flops propagates to the output’. This propagation is termed as state transition. As shown in figure 1, the ‘2-bit’ ring counter transitions from state ‘01’ to ‘10’ on active clock edge.

Figure 1: Figure showing state transition on active edge of clock

Clock signals occupy a very important place throughout the chip design stages. Since, the state transition happens on clock transition, the entire simulations including verification, static timing analysis and gate level simulations roam around these clock signals only. If Static timing analysis can be considered as a body, then clock is its blood. Also, during physical implementation of the design, special care has to be given to the placement and routing of clock elements, otherwise the design is likely to fail. Clock elements are responsible for almost half the dynamic power consumption in the design. That is why; clock has to be given the prime importance.

Clock tree: A clock signal originates from a clock source. There may be designs with a single clock source, while some designs have multiple clock sources. The clock signal is distributed in the design in the form of a tree; leafs of the tree being analogous to the sequential devices being triggered by the clock signal and the root being analogous to the clock source. That is why; the distribution of clock in the design is termed as clock tree. Normally, (except for sometimes when intentional skew is introduced to cater some timing critical paths), the clock tree is designed in such a way that it is balanced. By balanced clock tree, we mean that the clock signal reaches each and every element of the design almost at the same time. Clock tree synthesis (placing and routing clock tree elements) is an important step in the implementation process. Special cells and routing techniques are used to ensure a robust clock tree.

Clock domains: By clock domain, we mean ‘the set of flops being driven by the clock signal’. For instance, the flops driven by system clock constitute system domain. Similarly, there may be other domains. There may be multiple clock domains in a design; some of these may be interacting with each other. For interacting clock domains, there must be some phase relationship between the clock signals otherwise there is chance of failure due to metastability. If phase relationship is not possible to achieve, there should be clock domain synchronizers to reduce the probability of metastability failure.

Specifying a signal as clock: In EDA tools, ‘create_clock’ command is used to specify a signal as a clock. We have to pass the period of the clock, clock definition point, its reference clock (if it is a generated clock as discussed below), duty cycle, waveform etc. as argument to the command.

Master and generated clocks: EDA tools have the concept of master and generated clocks. A generated clock is the one that is derived from another clock, known as its master clock. The generated clock may be of the same frequency or different frequency than its master clock. In general, a generated clock is defined so as to distinguish it from its master in terms of frequency, phase or domain relationship. 

Some terminology related to clock: There are different terms related to clock signals, described below:

•      Leading and trailing clock edge: When clock signal transitions from ‘0’ to ‘1’, the clock edge is termed as leading edge. Similarly, when clock signal transitions from ‘1’ to ‘0’, the clock edge is termed as trailing edge.

• Launch and capture edge: Launch edge is that edge of the clock at which data is launched by a flop. Similarly, capture edge is that edge of the clock at which data is capture by a flop.
• Clock skew: Clock skew is defined as the difference in arrival times of clock signals at different leaf pins. Considering a set of flops, skew is the difference in the minimum and maximum arrival times of the clock signal. Global skew is the clock skew for the whole design. On the contrary, considering only a portion of the design, the skew is termed as local skew.

 Also read:

• Virtual clock
• Clock latency
• How to make clock glitch-free
• Metastability
• Synchronization schemes in VLSI design

Setup check and hold check for flop-to-latch timing paths

In the post (Setup and hold – basics of timinganalysis), we introduced setup and hold timing requirements and also discussed why these requirements are needed to be applied. In this post, we will be discussing how these checks are applied for different cases for paths starting from flops and ending at latches and vice-versa.

Present day designs are focused mainly on the paths between flip-flops as the elements dominating in them are flip-flops. But there are also some level-sensitive elements involved in data transfer in current-day designs. So, we need to have knowledge of setup and hold checks for flop-to-latch and latch-to-flop paths too. In this post, we will be discussing the former case. In totality, there can be total 4 cases involved in flop-to-latch paths as discussed below:

1)                  Paths launching from positive edge-triggered flip-flop and being captured at positive level-sensitive latch: Figure 1 shows a path being launched from a positive edge-triggered flop and being captured on a positive level-sensitive latch. In this case, setup check is on the same rising edge (without time borrow) and next falling edge (with time borrow) and hold check on the previous falling edge with respect to the edge at which data is launched by the launching flop.

Figure 1: Timing path from positive edge flop to positive level latch

Figure below shows the waveforms for setup and hold checks in case of paths starting from a positive edge triggered flip-flop and ending at a positive level sensitive latch. As can be figured out, setup and hold check equations can be described as:

            T_ck->q + T_prop + T_setup < T_skew + T_{period/2                                (for setup check)}

            T_ck->q + T_prop > T_hold + T_skew    - (T_period/2)                       _{(for hold check)}

2)                  Paths launching from positive edge-triggered flip-flop and being captured at negative level-sensitive latch: Figure 3 shows a path starting from positive edge-triggered flip-flop and being captured at a negative level sensitive latch. In this case, setup check is on the next falling edge (without time borrow) and on next positive edge (with time borrow). Hold check on the same edge with respect to the edge at which data is launched (zero cycle hold check).

 

Figure 3: Path from positive edge flop to negative level latch

Figure below shows the waveforms for setup and hold checks in case of paths starting from a positive edge triggered flip-flop and ending at a negative level-sensitive latch. As can be figured out, setup and hold check equations can be described as:

            T_ck->q + T_prop + T_setup < (T_period) + T_{skew                        (for setup check)}

            T_ck->q + T_prop > T_hold + T_{skew                                                   (for hold check)}

 

3)                  Paths launching from negative edge-triggered flip-flop and being captured at positive level-sensitive latch: Figure 5 shows a path starting from negative edge-triggered flip-flop and being captured at a positive level sensitive latch. In this case, setup check is on the next rising edge (without time borrow) and next falling edge (with time borrow). Hold check on the next rising edge with respect to the edge at which data is launched.

 

Figure 5: Path from negative edge flop to positive level latch

Figure below shows the waveforms for setup and hold checks in case of paths starting from a negative edge triggered flip-flop and ending at a positive level-sensitive latch. As can be figured out, setup and hold check equations can be described as:

            T_ck->q + T_prop + T_setup < (T_period) + T_{skew                        (for setup check)}

            T_ck->q + T_prop > T_hold + T_{skew                                                   (for hold check)}

1)                  Paths launching from negative edge-triggered flip-flop and being captured at negative level-sensitive latch: Figure 5 shows a path starting from negative edge-triggered flip-flop and being captured at a negative level sensitive latch. In this case, setup check is on the same edge (without time borrow) and on next rising edge (with time borrow). Hold check on the next rising edge with respect to the edge at which data is launched.

 

Figure 5: Path from negative edge flop to negative level latch

Figure below shows the waveforms for setup and hold checks in case of paths starting from a negative edge triggered flip-flop and ending at a negative level-sensitive latch. As can be figured out, setup and hold check equations can be described as:

            T_ck->q + T_prop + T_setup < T_period/2 + T_{skew                             (for setup check)}

            T_ck->q + T_prop > T_hold + T_skew   - (T_period/2)                       _{(for hold check)}