Setup check and hold check for flop-to-latch timing paths



In the post (Setup and hold – basics of timinganalysis), we introduced setup and hold timing requirements and also discussed why these requirements are needed to be applied. In this post, we will be discussing how these checks are applied for different cases for paths starting from flops and ending at latches and vice-versa.
Present day designs are focused mainly on the paths between flip-flops as the elements dominating in them are flip-flops. But there are also some level-sensitive elements involved in data transfer in current-day designs. So, we need to have knowledge of setup and hold checks for flop-to-latch and latch-to-flop paths too. In this post, we will be discussing the former case. In totality, there can be total 4 cases involved in flop-to-latch paths as discussed below:
1)                  Paths launching from positive edge-triggered flip-flop and being captured at positive level-sensitive latch: Figure 1 shows a path being launched from a positive edge-triggered flop and being captured on a positive level-sensitive latch. In this case, setup check is on the same rising edge (without time borrow) and next falling edge (with time borrow) and hold check on the previous falling edge with respect to the edge at which data is launched by the launching flop.


Positive edge flop to positive level latch path

Figure 1: Timing path from positive edge flop to positive level latch


Figure below shows the waveforms for setup and hold checks in case of paths starting from a positive edge triggered flip-flop and ending at a positive level sensitive latch. As can be figured out, setup and hold check equations can be described as:
            Tck->q + Tprop + Tsetup < Tskew + Tperiod/2                                (for setup check)
            Tck->q + Tprop > Thold + Tskew    - (Tperiod/2)                       (for hold check)

Waveform showing setup check for positive flop to negative level latch is on next positive edge and hold check is on next negative edge.


2)                  Paths launching from positive edge-triggered flip-flop and being captured at negative level-sensitive latch: Figure 3 shows a path starting from positive edge-triggered flip-flop and being captured at a negative level sensitive latch. In this case, setup check is on the next falling edge (without time borrow) and on next positive edge (with time borrow). Hold check on the same edge with respect to the edge at which data is launched (zero cycle hold check).
 
Path starting from positive edge triggered flop and ending at negative level sensitive latch

Figure 3: Path from positive edge flop to negative level latch


Figure below shows the waveforms for setup and hold checks in case of paths starting from a positive edge triggered flip-flop and ending at a negative level-sensitive latch. As can be figured out, setup and hold check equations can be described as:
            Tck->q + Tprop + Tsetup < (Tperiod) + Tskew                        (for setup check)
            Tck->q + Tprop > Thold + Tskew                                                   (for hold check)
Setup check for positive flop to negative level latch is on next positive edge and hold check is on next negative edge.

 
3)                  Paths launching from negative edge-triggered flip-flop and being captured at positive level-sensitive latch: Figure 5 shows a path starting from negative edge-triggered flip-flop and being captured at a positive level sensitive latch. In this case, setup check is on the next rising edge (without time borrow) and next falling edge (with time borrow). Hold check on the next rising edge with respect to the edge at which data is launched.
 
Path starting from negative edge triggered flip-flop and ending at positive level sensitive latch

Figure 5: Path from negative edge flop to positive level latch


Figure below shows the waveforms for setup and hold checks in case of paths starting from a negative edge triggered flip-flop and ending at a positive level-sensitive latch. As can be figured out, setup and hold check equations can be described as:

            Tck->q + Tprop + Tsetup < (Tperiod) + Tskew                        (for setup check)
            Tck->q + Tprop > Thold + Tskew                                                   (for hold check)


Setup check for positive flop to negative level latch is on next positive edge and hold check is on next negative edge.

1)                  Paths launching from negative edge-triggered flip-flop and being captured at negative level-sensitive latch: Figure 5 shows a path starting from negative edge-triggered flip-flop and being captured at a negative level sensitive latch. In this case, setup check is on the same edge (without time borrow) and on next rising edge (with time borrow). Hold check on the next rising edge with respect to the edge at which data is launched.

 
Path starting from negative edge-triggered flop and ending at negative level-sensitive latch

Figure 5: Path from negative edge flop to negative level latch

Figure below shows the waveforms for setup and hold checks in case of paths starting from a negative edge triggered flip-flop and ending at a negative level-sensitive latch. As can be figured out, setup and hold check equations can be described as:
            Tck->q + Tprop + Tsetup < Tperiod/2 + Tskew                             (for setup check)
            Tck->q + Tprop > Thold + Tskew   - (Tperiod/2)                       (for hold check)


Setup check for positive flop to negative level latch is on next positive edge and hold check is on next negative edge.

13 comments:

  1. Hi

    This is just basic blogger theme with some customizations. Let me know if you need some help.

    ReplyDelete
  2. Amazing. Thank u for sharing this!

    ReplyDelete
  3. Amazing post, thank you for sharing this. So useful!

    ReplyDelete
  4. how could I get more detailed thing about this

    ReplyDelete
    Replies
    1. Hi

      I guess following post will be useful for you.

      https://vlsiuniverse.blogspot.com/2016/12/setup-hold-interview-questions.html

      Delete
  5. Hi,

    For the case of positive edge-triggered FF to positive level-sensitive latch, why does the setup check (without time borrow) happen on same edges of launch and capture clock. Isn't the intended logic that the data launched on active edge of launch clock be captured on the next active edge (low-to-high in this case) of capture clock? Or am I not understanding the functionality of the design correctly? Please advise.

    ReplyDelete
    Replies
    1. Hi

      In case of latch, there is an active level (not active edge). This, in case of a positive latch, ranges from positive edge to negative edge. So, data can be captured anywhere in between.

      Delete
    2. Still should the capture not be in next active level instead of same active level?

      Delete
    3. I feel this post should be helpful to you. :-) Please provide feedback on it.

      https://vlsiuniverse.blogspot.com/2020/11/how-to-interpret-default-setup-and-hold.html

      Delete
    4. Yeah, I think its incorrect. you should check it in the next cycle for setup time. If you are checking in the same cycle then there should be no hold violations in case 2 and 4. Please edit the post or clarify it.

      Delete
  6. This is really good!

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  7. Great post! Thank you for this detailed analysis. Can you comment on the pros/cons of using time borrowing? In my understanding, you show that time borrowing gets you an extra 0.5 cycle on the setup check which could make timing easier to meet. On the other hand, it looks like time borrowing would allow Latch/Q to potentially be glitchy since Latch/D is allowed to change while the latch is transparent. If it's direct FF -> Latch with no combo logic in between then this is probably ok because you will only have 1 transition at Latch/D per clock cycle. However, if there is combo logic in between, (i.e., FF -> Combo -> Latch), then you could have many transitions at Latch/D per clock cycle which means power consumption could be increased if Latch/Q is driving any downstream logic. What are your thoughts on that? And are there any other pros/cons that you see with using time borrowing for FF -> Latch capture?

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    Replies
    1. Hi

      True, but i dont it will be too much to bother about.

      Remember, a flop is 2 latches in series. So by using a latch, we are saving area and power equivalent to half a flop as well.

      And its only the output of latch that will toggles extra. If it had been a flop, all kogic upto flop input would have toggled as well for wach of the target cases.

      Delete

Thanks for your valuable inputs/feedbacks. :-)