LVS in VLSI

LVS stands for Layout vs Schematic. It is one of the steps of physical verification; the other one being DRC (Design Rule Check). While DRC only checks for certain layout rules to ensure the design will be manufactured reliably, functional correctness of the design is ensured by LVS.

Layout vs Schematic (LVS) compares the design layout with the design schematic/netlist to tell if the design is functionally equivalent to schematic. For this, the connections are extracted from layout of the design by using a set of rules to convert the layout to connections. These connections are, then compared if they match with the connections of the netlist. If the connections match, the LVS is said to be clean. 

VLSI - 2 ( Analog)

For those of you who wanted to make a career in analog, be a devotee of IIT Madras faculty irrespective of which IIT or which college you end up joining for your Mtech.

1. Shanti Pavan - IIT Madras videos
2. Nagendra Krishnapura - IIT Madras videos
3. Razavi - Videos and Text book
4. Anirudhan  - IIT Madras videos

I would like to discuss few common blunders, that we end up doing, which henceforth make us loose confidence in analog


Mistake 1 :  Two current sources in series

In simulation if you put two current sources in series and simulate this, you observe some crazy things happen, kindly do this and learn on this.



Put up a current source with NMOS sinking the current with very low Vgs and observe

Repeat the experiment with PMOS too. Try increasing the sizing for the same Vgs and observe what happens.

This experiments are really the most powerful in analog. The deeper one digs into this, the faster he understands the analog concepts well.

Spend great time dealing with this circuit.

Feel free to discuss if any doubts.......

Will come back with the next post. and discuss the solution and concepts here.