VLSI UNIVERSE

No posts with label INFOSYS TRAINING MYSORE GENERIC STREAM. Show all posts

No posts with label INFOSYS TRAINING MYSORE GENERIC STREAM. Show all posts

Subscribe to: Posts (Atom)

Popular Posts

Setup time and hold time basics

In digital designs, each and every flip-flop has some restrictions related to the data with respect to the clock in the form of window...
2-input gates using 2:1 mux

Definition of a multiplexer : A 2^n-input mux has n select lines. It can be used to implement logic functions by implementing LUT (Look-Up...
Regions of operation of MOS transistors

A Metal Oxide Semiconductor Field Effect Transistors (MOSFET, or simply, MOS) is a four terminal device. Figure 1 below shows the gene...
Lockup latch – principle, application and timing

What are lock-up latches : Lock-up latch is an important element in scan-based designs, especially for hold timing closure of shift modes....
2 bit Binary multiplier

Binary multiplication process : A Binary Multiplier is a digital circuit used in digital electronics to multiply two binary numbers and p...
Synchronizers

Modern VLSI designs have very complex architectures and multiple clock sources. Multiple clock domains interact within the chip. Also,...
2x1 mux using NAND gates

As we know, the logical equation of a 2-input mux is given as below: Y = (s' A + s B) Where s is the sele...
4x1 mux using NAND gates

In the post 2x1 mux using NAND gates , we discussed how we can use NAND gates to build a 2x1 multilexer. In this post, we will discuss how ...
Clock gating checks

Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. ...
Latchup and its prevention in CMOS devices

What is Latchup : Latchup refers to short circuit formed between power and ground rails in an IC leading to high current and damage to the...

Blog Archive

▼ 2023 (1)
- ▼ May (1)
  - Does inserting lockup latch affect Logic Equivalen...

► 2022 (3)
- ► December (3)

► 2020 (21)
- ► November (1)
- ► August (3)
- ► July (2)
- ► June (1)
- ► May (3)
- ► April (7)
- ► March (3)
- ► February (1)

► 2019 (21)
- ► November (2)
- ► October (2)
- ► September (2)
- ► July (3)
- ► June (3)
- ► May (1)
- ► April (1)
- ► March (6)
- ► February (1)

► 2018 (7)
- ► December (1)
- ► September (1)
- ► August (2)
- ► July (1)
- ► May (1)
- ► January (1)

► 2017 (43)
- ► December (5)
- ► November (4)
- ► October (7)
- ► September (1)
- ► August (4)
- ► April (2)
- ► March (7)
- ► February (6)
- ► January (7)

► 2016 (74)
- ► December (16)
- ► November (12)
- ► October (10)
- ► September (7)
- ► August (4)
- ► July (6)
- ► June (6)
- ► May (5)
- ► April (8)

► 2015 (31)
- ► September (2)
- ► August (2)
- ► June (23)
- ► May (1)
- ► April (3)

► 2014 (19)
- ► December (4)
- ► November (2)
- ► August (3)
- ► July (4)
- ► June (1)
- ► May (3)
- ► April (1)
- ► January (1)

► 2013 (26)
- ► October (1)
- ► September (5)
- ► August (4)
- ► July (5)
- ► June (2)
- ► May (6)
- ► March (1)
- ► February (1)
- ► January (1)

► 2012 (1)
- ► December (1)

Labels

STA Design basics Static timing analysis VLSI Digital system design Interview Questions Digital electronics setup check LST PRG timing basics CMOS basics DFT IQ hold check setup and hold Clock gating interview questions Physical design STA interview questions clock gating VLSI TRIVIA programming Static Timing Analysis Interview Questions computer trivia C++ Metastablity Puzzles asynchronous reset fsm launch edge setup AND type clock gating Clock Jitter Clock jitter in VLSI Digital Lockup latch Low power design Physica design analog clock gating check duty cycle variation finite state machine half cycle jitter latch multicycle path multiplexer propagation delay scripting shellbr time borrow timing vhdl 2-bit binary multiplier 2:1 mux ADC CMOS Clock gating cell Clock mux Cycle to cycle jitter Duty cycle of clock. Clock duty cycle ECO LVS Mux applications NOR gate using mux OCV RC corner Resolve setup violations STA analysis STA basics Setup and hold time concepts Synchrounous vs asynchronous reset Timing closure interview questions Trivia VDTT XOR gate using mux analog to digital converter base eco binary multiplier capture edge clock clock glitch clock skew clock switching controllability data checks delay variation depletion MOSFET digital design enhancement MOSFET false path flip-flop frequency function hold hold time latch principle latency metal eco multi cycle path multicycle mux net arc noise observabilty on chip variations setup time synchronization test principles -end -start 16 1 mux using 4 1 muxes 16-input multiplexer 16-input multiplexer using 4-input multiplexers 16:1 mux 16:1 mux using 4:1 muxes 2 bit by 2 bit binary multiplier 2 bit multiplier using logic gates 2-input NOT gate using 2:1 mux 2-input XNOR gate using NAND gates 2-input mux 2x1 mux 3 inputs mux 3-input AND gate using 2:1 mux 3-input OR gate using 2:1 mux 4-bit carry look ahead adder 4-input mux 4:1 mux 4:1 mux from NAND gates 4x1 mux 8-input mux 8:1 mux 8x1 mux AND gate AND gate using mux AND gate with multiplexer Anirudhan Array and linked list comparison Binary multiplier in digital circuits Binary to thermometer code Binary to thermometer code converter Binary to thermometer decoder Bubble error Bubble error correction C++ Integer to string conversion C++ master C++ string to integer conversion C++ trivia CEDT Flip flop written test Carry bypass adder Carry look ahead adder advantages Carry look ahead adder truth table Cell delay VLSI Clock buffer Clock clipping Clock divider VHDL Clock divider VHDL code Clock gate Clock gate cell Clock gating check example Clock gating for power saving Clock gating in VLSI Clock gating latch Clock gating must read Clock gating timing check Clock insertion Delay Clock multiplexer Clock multiplier Conductivity vs temperature Configurable clock divider VHDL Controllable and observable D-latch using mux DFT in VLSI DFT interview questions DRC Data buffer Data hold time Data setup time Define set up time Define setup time Define virtual clock Delay in VLSI Delay in logic gates Depletion mode MOSFET Design 16 1 mux using 4 1 muxes Difference between clock buffer and data buffer Difference between enhancement and depletion MOSFET Difference between setup time and hold time Digital electronics interview questions Drive strength Drive strength of logic gates ECE MTECH PACKAGE CORE ECO VLSI ECO engineering change order ECO in VLSI Engineering Change Order Definition Engineering Change Orders Engineering change order Enhancement mode MOSFET Everything about clock gating FIFO False path constraint False path in digital design Fixing hold violaitons Fixing minimum pulse width violations Flip-flop setup time GATE Preparation Gate propagation delay time Glitchfree clock gating Hold critical paths Hold slack calculation Hold time meaning Hold time violation Hold time violations Hold violation How drive strength impacts delay How to avoid setup and hold time violations How to solve setup and hold violations IC latchup ICG cell ICG clock gating IISCBangalore CEDT AIR IIT BOMBAY RA AIR 295 IIT BOMBAY TA RA AIR IIT Madras IITKharagpur INFOSYS TRAINING MYSORE GENERIC STREAM Implementatin of XNOR gate using NAND gates Implementation Improving the duty cycle of clock Insertion delay Integrated clock gating Jitter K-map LBIST Latch applications Latch phenomenon Latch setup and hold Latch setup time Latch up CMOS Latch up VLSI Latch up condition Latch up current Latch up definition Latch up effect Latch up in MOSFET Latch using 2-input mux Latch using 2x1 mux Latch using multiplexer Latch using mux Latchup prevention Logic race condition Long term jitter MBIST basics MBIST test MOS transistor operation MOSFET MOSFET depletion mode MOSFET operating regions MS DIRECT PHD MTBF Make header dependencies Makefile header dependencies Makefile include dependencies Meaning of unateness Memory BIST Memory Self Test Metastability in VLSI Metastability in digital design Meyer singleton Meyers singleton Multicycle constraint example Multiply by 2 NAND gate applications NAND gate using mux NAND to XOR NAND vs NOR NMOS current equation NOT gate using mux NagendraKrishnapura Need of virtual clock Negative delay Negative gate delay Negative hold time Negative propagation delay Negative set up time Negative setup Negative setup time Negative unate Net delay Net propagation delay Network latency Meaning Node observability Non-observable OR gate OR gate usin mux OR gate using mux OR type clock gating OR type clock gating check PVT corner PVT in VLSI PVT variations Period Jitter Positive hold time Positive setup time Positive unate Propagation delay VLSI Propagation delay example Propagation delay in logic gates Propagation delay time Pulse generator Race condition Razavi Recovery check Removal check Reset basics Reset deassertion timing Reset strategies Reset synchronizer circuit Resolve hold violations SDC commands STL Set up time Set up time definition Setup and hold checks for latch Setup and hold time violations example Setup and hold times for latch Setup check example Setup critical paths Setup hold example Setup slack calculation Setup time and hold time Setup time definition Setup time in flip-flop Setup time violation Setup time violations Setup timing path Example Setup violation Setup violations Shanthi Pavan Skew check Skew checks with the help of data checks Skew in VLSI Spare cell Spare cells in VLSI Standard cells Static Timing Analysis Basics Static Timing Analysis problems Synchronizers in VLSI Synchronizers in digital circuits TG TG gates TGs TI MS Texas IIT MADRAS vlsi Temperature inversion CMOS Temperature inversion VLSI Temperature inversion phenomenon Thermometer code Thermometer encoding Time borrowing Timing arc Timing path Transmission gate theory Transmission gates working Types of clock skew VDTT IEC VLSI VDTT JTM CMOS VHDL clock divider VHDL code for binary to thermometer converter VHDL code for divider VHDL code for frequency divider VHDL interview questions VLSI interview questions for freshers Virtual clock Virtual clock SDC Virtual clock STA Virtual clock VLSI Virtual clock example What is VLSI What is clock gating What is latchup What is metastability What is synchronizer What is transmission gate Why is signleton an anti pattern XNOR gate implementation XNOR gate using mux XNOR using NAND XNOR using NAND gates XNOR using mux XOR gate XOR gate applications XOR gate using NAND XOR gate with NAND gates XOR using NAND XOR using NAND gates XOR using mux Zero cycle hold check Zero cycle timing path Zero hold time Zero setup time Zerocycle paths admissions alert iit mtech types ra ta phd direct phd analog design array carry look ahead adder cell arc cell delay cell delay variation circuit to multiply 2-bit numbers clk divider vhdl clock at complex gate clock domain clock latency clock muxing common body common substrate computer technology JTM VDTT JVL IEC control point counter cut-off cypress semiconductors data check data hold check data invalid window data setup check data structure data to data checks data valid window delay variationn depletion design for testability does jitter impact hold does jitter impact setup fabrication false path example false paths flash ADC flip-flop synchronizer flop-based synchronizer frequency dependant hold function overloading generated clock generic stream infosys training mysore pressure pleasure glitch free clock gating half cycle paths high frequency designs implement function using mux integrated clock gating cell kanpur iit latch timing latch up latchup latchup in MOSFET launch clock leading edge linear operation of MOS linear region linked list lockup register logic families logic gates master clock mbist metastability method signature minimum pulse width minimum pulse width check multi cycle multi cycle path setup hold multi-cycle multi-cycle path multicycle path example multiplier mux-based synchronizer negative level latch network latency newiit iit hyderabad ta ra nmos noise margin non-default hold non-unate observe points overloading parasitics pmos positive level latch receiver recovery and removal checks reset assertion reset deassertion routing rtl design saturation scan chains scan flop semiconductor conductivity sequential design series currentsources set clock gating check set clock latency set false path set false path example set multicycle path set_clock_latency set_data_check set_false_path set_min_pulse_width set_multicycle_path setup checks and hold checks setup hold check signoff skew spare cells synchronizer synchronizer circuit synchronous reset tcl temperature inversion texas qualcomm cadence interview throughput timing arcs timing sense transmission gates transmitter types of clock gating checks unate unateness vector voltage why hold check is on same edge why setup check is on next edge wire width world worst slew propation x-propagation xnor gate using 2x1 mux xor gate using 2x1 mux

Categories

[accordion] [item title="Title Of Tab 1"] INSERT CONTENT HERE [/item] [item title="Title Of Tab 2"] INSERT CONTENT HERE [/item] [item title="Title Of Tab 3"] INSERT CONTENT HERE [/item] [/accordion]

Sponsored ad

Sponsored ad

TOP SITES

VLSI Logic Design Interview Questions
** VLSI WORLD
Software in layman language

Translate

Total Pageviews

Contact Form

Name

Email *

Message *

Powered by Blogger.