Interview questions related to reset design and reset timing

Below we list few of our posts related to reset timing and some design concepts related to reset. Happy learning.

Reset basics - Discusses the purpose and design strategies related to reset

Synchronous and asynchronous resets - Discusses the basics of synchronous reset and asynchronous reset. Also discusses few differences between them

Reset synchronizer - Discusses the definition, need and working of reset synchronizers.

Recovery and removal checks - Discusses the timing aspects of asynchronous reset. Provides the definition of recovery check, removal check, recovery time and removal time.

Asynchronous reset assertion timing scenarios - Discusses if there may arise a need to time the assertion of asynchronous resets

Duty cycle care-abouts for clock paths in reset assertion - Discusses how reset assertion can alter the duty cycle of clock, and what needs to be taken care of.

Our purpose is to make this page a single destination for any questions related to reset design and timing. If you have any source of educational information related to reset, please comment or send an email to myblogvlsiuniverse@gmail.com and we will add it here. Also, feel free to ask any question related to reset design and timing.

Logic design interview questions

• BCD multiply by five circuit

• 2-bit binary multiplier

• Implement 3 and 4 variable functions using 8:1 mux

• 16x1 mux using 4x1 muxes

• Delay line based time-to-digital converter

• How to build an XOR gate with NAND gates

• Multiply by 2 clock circuit

• Implement 3-input gates using 2x1 muxes

• Divide by 2 clock in VHDL

• 3-input AND gate using 4:1 mux

• 2x1 mux using NAND gates

• XNOR gate using NAND

• 8x1 multiplexer using 4x1 multiplexers

• Reset basics

VHDL

Listing below the posts related to VHDL and HDL coding. Please provide your feedback in comments as to what more posts you wish to see here:

• Defining a clock signal in VHDL

• Delay line based Time-to-Digital converter

• VHDL code for configurable divider

DFT basics

DFT stands for Design For Testification. DFT engineers try to make the testing of design more cost effective by introducing some structures into the design itself. By doing so, the overall test cost, and hence, cost of production comes down. Below, we list some of our posts covering the basics of DFT. Please provide your feedbacks regarding the topics you want to see as a part of this list. :-) Happy learning.

• Controllability and observability - basics of DFT

• Scan chains

• Lockup latches - basics and timing scenarios

• Lockup latches vs lockup registers - what to choose

• MBIST (Memory Built-In Self Test)

• LBIST (Logic Built-In Self Test)

Setup and hold interview questions

Almost every interview for a VLSI design engineer has at least a question related to setup and hold. So, it is very important to prepare well. We list below a few topics related to setup and hold that may prove to be more than useful for setup and hold related interview questions.

• Setup time

• Positive, negative and zero setup time

• Hold time

• Positive, negative and zero hold time

• STA problem : hold time manipulation

• Setup time vs hold time

• Setup checks and hold checks

• Can hold check be frequency dependent?

• What makes a timing path both setup and hold timing critical

• Setup and hold violations

• How to fix setup violations

• How to fix hold violations

• How multicycle paths manipulate setup and hold checks

• Setup and hold times for latches

• Concept of time borrowing in latches

• STA problem: what is the maximum frequency following circuit can work at?

• STA problem: can you figure out if there is any setup/hold violation in the circuit?

• STA problem : Modeling skew requirements with the help of data-to-data checks

• Data checks - all about data setup and data hold check

• Clock gating checks

• Clock gating checks at a multiplexer

Please share your interview experiences with us in comments so that these can be of help to other readers. Also, if you have any suggestion for us, you can get in touch with us. All the best. :-)

Clock gating interview questions

One of the most important and frequently asked topics in interviews is clock gating and clock gating checks. We have a collection of blog-posts related to this topic which can help you master clock gating. You can go through following links to add to your existing knowledge of clock gating:

• Clock gating - basics: Discusses the basic concept and principle of clock gating

• How clock gating saves dynamic power: Discusses how dynamic power is saved with clock gating

• Need for clock gating checks: Discusses why clock gating checks are needed for glitchless propagation of clock

• Clock gating checks: Discusses different clock gating structures used and associated timing checks related to these

• Clock gating checks at a mux: Discusses clock gating checks that should be applied in case one of the inputs of mux has a clock signal connected to it, which is the most common clock gating check in today's designs

• Quiz: Clock gating checks at a complex gate: Discusses how to proceed if there is a random combinational cell having a clock at one of its inputs

• Integrated clock gating cell: Discusses the special clock gating cell used in designs to implement clock gating in today's designs

• Can we use discrete latches and AND/OR gates instead of ICG? : Discusses the advantages of using integrated clock gating cell, instead of discrete AND/OR gates and latches.

• Clock multiplexer for glitch-free clock switching: Discusses the structure of glitchless mux. 

• Design problem: Clock gating for a shift register: Discusses how we can clock gate a complete module with the help of a simple example.

• Clock gating checks in case of mux select transition when both clocks are running: A design example showing complex application of clock gating checks

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Our purpose is to make this page a single destination for any questions related to clock gating. If you have any source of related and additional information, please comment or send an email to myblogvlsiuniverse@gmail.com and we will add it here. Also, feel free to ask any question related to clock gating.

Puzzles and brainteasers

A lot of questions in interviews are related to puzzles and brainteasers and are meant to relate to the thought process of the candidate. Listing below a few of the puzzles that may be of interest to you.

• Measure time using candles!!

• Matchstick game bonanza!!

Please feel free to share puzzles that you think may be of interest to others. 

STA

Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circuit without actually simulating it. In this post, we have tried to list down all the posts that an STA engineer cannot do without. Please add your feedback in comments to make reading it a more meaningful experience.

• Setup and hold interview questions

• Clock gating concepts
• Setup time and hold time - static timing analysis - Definition and detailed discussion on setup time and hold time, setup hold violations and how to fix them

• Metastability - This post discusses the basics of metastability and how to avoid it.

• Problem: clock gating checks at a complex gate - An exercise to analyze the requirements of clock gating checks at a complex gate

• Lockup latch - The basics of lockup latch, both from timing and DFT perspective have been discussed in this post.

• Lockup latches vs. lockup registers - Provides an insight into the situations where lockup latches and lockup registers can be useful.

• Clock latency - Read this if you wish to get acquainted with the terminology related to clock latency

• Data checks - Non-sequential setup and hold checks have been discussed, very useful for beginners

• Modeling skew requirements with the help of data checks - Explains with an example how data checks can be used to maintain skew requirements

• What is static timing analysis - Defines static timing analysis and its scope

• Setup checks and hold checks for reg-to-reg paths - Discusses the default setup and hold checks for timing paths starting from and ending at registers

• Setup checks and hold checks for register-to-latch paths - Discusses the default setup and hold checks for timing paths starting from registers and ending at latches

• Setup checks and hold checks for latch-to-reg timing paths - Discussed the default setup and hold checks for timing paths starting from latches and ending at registers

• All about clock signals - Discusses the basics of clock signals

• Synchronizers - Different types of synchronizers have been discussed in detail

• Timing corners - dimensions in timing signoff - Highlights the importance of signing off in different corner-case scenarios

• Ensuring glitch-free propagation of clock - Discusses about the hazards that can occur, if there is a glitch in clock

• Clock switching and clock gating checks - The basics of clock gating check, and how to apply these is discussed

• Clock gating checks at a mux - How clock gating checks should be applied on a mux is discussed in detail

• False paths - what are they - This post discussed the basics of false paths and how to treat them

• Multicycle paths handling in STA - Basics of multicycle paths and how they are treated in STA

• All about multicycle paths in VLSI - Architecture specific description and handling of multicycle paths, a must read

• Propagation delay - Defines propagation delay and related terms

• Is it possible for a logic gate to have negative delay - Thought provoking post on whether a logic gate can have negative delay

• Worst slew propagation - Discusses the basics of worst slew propagation

• On-chip variations - Describes on-chip variations and the methods undertaken to deal with these

• Temperature inversion - Discusses the concept of temperature inversion and conductivity trends with temperature

• Can a net have negative delay - Describes how a net cannot have a negative delay

• Timing arcs - Discusses the basics of timing arcs, positive and negative unateness, cell arcs and net arcs etc.

• Time borrowing in latches - Discusses the basics of the concept of time borrowing

• Interesting problem - latches in series - Describes why it is essential to have alternate positive and negative latches for sequential operation

• Virtual clock - Explains the concept of virtual clock

• Minimum pulse width - Discusses about minimum pulse width checks

• Basics of latch timing - Definition of latch, setup time and hold timing of a latch, latch timing arcs are discussed

VLSI design interview questions

VLSI stands for Very Large Scale Integration and it enables the creation of integrated circuits by incorporating thousands, and even millions of transistors on a single chip. Before VLSI, only small functionalities could be integrated onto a chip. Most of the ICs could perform only a small set of functions such as ALU, counters etc. With the help of VLSI technology, it has become possible to get a whole system designed on a single chip.

Getting into the field of VLSI demands knowledge of some of the basic concepts, be it systems design, timing analysis, RTL design etc. We have tried to collate a few of the topics in the links below. Going through these should be helpful for you. Looking for your feedback for further improvement.

• Static timing analysis (STA) interview questions

• DFT interview questions

• VHDL interview questions