Can jitter in clock effect setup and hold violations?

First of all, we need to understand what is meant by jitter. In most simplistic language, jitter is the uncertainty of a clock source in production of clock edges. For example, if we say that there is a 100 MHz clock source. Ideally, it should produce a clock edge at 0 ns, 10 ns, 20 ns... So, if we say that there was a clock edge at time t = 30 ns, we should get the next clock edge at t = 40 ns. But this is hardly so; due to the uncertainty of getting a clock edge, we might get the next edge between 39.9 ns to 40.1 ns. So, we say that 0.1 ns is the jitter in the period of the clock. In reality, the definition of jitter is more complex. But, for our scope, this understanding is sufficient.

Let us consider a simple timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop.

Now, let us come to our discussion. First, let us discuss the effect of clock jitter on setup slack.

Effect of clock jitter on setup slack for single cycle paths: From our knowledge of STA basics, setup check formed, in this case, will be from edge 1 -> edge 3. Now, if we know that edge 1 arrived at 20 ns, then edge 3 may arrive at any time (20 ns + CLOCK_PERIOD + jitter) and (20 ns + CLOCK_PERIOD - jitter). So, to cover worst case timing scenario, we need to time as per (20 ns + CLOCK_PERIOD - jitter). So, effectively, we will get (CLOCK_PERIOD - jitter) as effective clock period.

In other words, jitter in clock period makes the setup timing more tight. Or it decreases setup slack for single cycle timing paths.


Effect of clock jitter on hold slack for single cycle paths: Going on the same grounds as setup slack, hold check will be from edge 1 -> edge 1 only. And we know with certainty that edge 1 will leave the source at 20 ns only. So, hold slack should not get bothered by the amount of jitter present at the clock source for single cycle timing paths.

Now, you understand the basics of  how jitter affects setup and hold slacks. We can state as below:

If the check being formed involves two different edges of same polarity (for instance, different rising edges), then, jitter in clock period will affect setup slack. Otherwise, it will not.

Now, can you guess the effect of jitter on setup and hold slacks for zero cycle timing paths?

Also, what will be the amount of pessimism needed to be taken into account for setup and hold slacks' calculations if the timing path is a multi-cycle path taking 2 cycles for setup and zero cycle for hold?

Also read:

• Interview questions related to clock jitter and duty cycle variations

STA

Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circuit without actually simulating it. In this post, we have tried to list down all the posts that an STA engineer cannot do without. Please add your feedback in comments to make reading it a more meaningful experience.

• Setup and hold interview questions

• Clock gating concepts
• Setup time and hold time - static timing analysis - Definition and detailed discussion on setup time and hold time, setup hold violations and how to fix them

• Metastability - This post discusses the basics of metastability and how to avoid it.

• Problem: clock gating checks at a complex gate - An exercise to analyze the requirements of clock gating checks at a complex gate

• Lockup latch - The basics of lockup latch, both from timing and DFT perspective have been discussed in this post.

• Lockup latches vs. lockup registers - Provides an insight into the situations where lockup latches and lockup registers can be useful.

• Clock latency - Read this if you wish to get acquainted with the terminology related to clock latency

• Data checks - Non-sequential setup and hold checks have been discussed, very useful for beginners

• Modeling skew requirements with the help of data checks - Explains with an example how data checks can be used to maintain skew requirements

• What is static timing analysis - Defines static timing analysis and its scope

• Setup checks and hold checks for reg-to-reg paths - Discusses the default setup and hold checks for timing paths starting from and ending at registers

• Setup checks and hold checks for register-to-latch paths - Discusses the default setup and hold checks for timing paths starting from registers and ending at latches

• Setup checks and hold checks for latch-to-reg timing paths - Discussed the default setup and hold checks for timing paths starting from latches and ending at registers

• All about clock signals - Discusses the basics of clock signals

• Synchronizers - Different types of synchronizers have been discussed in detail

• Timing corners - dimensions in timing signoff - Highlights the importance of signing off in different corner-case scenarios

• Ensuring glitch-free propagation of clock - Discusses about the hazards that can occur, if there is a glitch in clock

• Clock switching and clock gating checks - The basics of clock gating check, and how to apply these is discussed

• Clock gating checks at a mux - How clock gating checks should be applied on a mux is discussed in detail

• False paths - what are they - This post discussed the basics of false paths and how to treat them

• Multicycle paths handling in STA - Basics of multicycle paths and how they are treated in STA

• All about multicycle paths in VLSI - Architecture specific description and handling of multicycle paths, a must read

• Propagation delay - Defines propagation delay and related terms

• Is it possible for a logic gate to have negative delay - Thought provoking post on whether a logic gate can have negative delay

• Worst slew propagation - Discusses the basics of worst slew propagation

• On-chip variations - Describes on-chip variations and the methods undertaken to deal with these

• Temperature inversion - Discusses the concept of temperature inversion and conductivity trends with temperature

• Can a net have negative delay - Describes how a net cannot have a negative delay

• Timing arcs - Discusses the basics of timing arcs, positive and negative unateness, cell arcs and net arcs etc.

• Time borrowing in latches - Discusses the basics of the concept of time borrowing

• Interesting problem - latches in series - Describes why it is essential to have alternate positive and negative latches for sequential operation

• Virtual clock - Explains the concept of virtual clock

• Minimum pulse width - Discusses about minimum pulse width checks

• Basics of latch timing - Definition of latch, setup time and hold timing of a latch, latch timing arcs are discussed