DFT stands for Design For Testification. DFT engineers try to make the testing of design more cost effective by introducing some structures into the design itself. By doing so, the overall test cost, and hence, cost of production comes down. Below, we list some of our posts covering the basics of DFT. Please provide your feedbacks regarding the topics you want to see as a part of this list. :-) Happy learning.
Showing posts with label DFT. Show all posts
Showing posts with label DFT. Show all posts
Lockup latches vs. lockup registers: what to choose
Both lockup latches and lockup
registers are used to make scan chain robust to hold failures. What one uses
for the same depends upon his/her priorities and the situation. However, it
seems lockup latches are more prevalent in designs of today. This might be due
to following reasons:
- Area: As we know, a latch occupies only half the area as a register. So, using lockup latches instead of lockup registers gives us area and power advantage; i.e., less overhead.
- Timing: Lockup elements – timing perspective has given an analysis of how timing critical lockup elements (lockup latches and lockup registers) paths can be. According to it, using a negative lockup latch, you don’t have to meet timing at functional (at-speed) frequency. However, in all other cases, you need to meet timing. This might also be a reason people prefer lockup latches.
Lockup latches, on one hand relax
only one side hold. So, you can afford to have skew only on one side, either on launch or
on capture. Lockup registers, on the other hand, let you have skew on both the
sides. So, lockup latches are preferable where you can afford to have tap on
the clock either from launch flop or on capture flop. On the other hand, lockup
flops can be used by tapping clock from any point as long as you meet setup and
hold timings.
Hope you’ve found this post useful. Let us know what you think in the comments.
How propagation of ‘X’ happens through different logic gates
‘X’ refers to a
signal attaining a value that is ‘unknown’. It can be either ‘0’ or ‘1’. But,
the exact value of the signal is not known. If a simulator is not able to decide
whether a logic value should be logic ‘0’ or logic ‘1’, it will assign a value ‘X’
to the value. An example of ‘X’ source is a logic block that has not been
initialized properly through reset. Having an ‘X’ value at a
node can propagate to the logic lying in the fan-out, thereby increasing the
uncertainty downstream the logic.
How ‘X’ propagates: An ‘X’ value
at the input of a logic gate may or may not propagate to its output depending
upon the states at other inputs of the logic gate. Given below is how different
logic gates react to ‘X’ values:
1) OR
gate: An OR gate can absorb an ‘X’ if the other input has logic ‘1’.
Otherwise, ‘X’ propagates through it. Please refer figure 1 for explanation:
 |
| Figure 1: X-propagation through OR gate |
2) AND
gate: An AND gate can absorb ‘X’ if the other input has logic ‘0’.
Otherwise, ‘X’ propagates through it. Please refer figure 2 for explanation:
 |
| Figure 2: X-propagation through AND gate |
3) Buffer/inverter:
Since, buffers/inverters are single input gates, an ‘X’ at the input means ‘X’
at the output.
4) XOR
gate: An ‘X’ at one of the inputs of XOR produces ‘X’ at the output no
matter what the
other input state is. Please refer truth table given in Figure 3 for explanation:
 |
| Figure 3: X-propagation through XOR gate |
5) Complex
gates: For complex gates, whether ‘X’ will propagate to the output
depends upon the overall function of the ‘X’ input with respect to other gates.
E.g. suppose a gate with function
Z = A + (B * C)
Then, if B input
goes ‘X’, the output will go ‘X’ if A=0 and C=1.
Read also:
What is Logic Built-in Self Test (LBIST)
LBIST stands for
Logic Built-In Self Test. As VLSI marches to deep sub-micron technologies,
LBIST is gaining importance due to the unique advantages it provides. LBIST
refers to a self-test mechanism for testing random logic. The logic can be
tested with no intervention from the outside world. In other words, a piece of
hardware and/or software is inbuilt into an integrated circuit to test itself. By
random logic, is meant any form of hardware (logic gates, memories etc.) that
can form a part or whole of the chip. A generic LBIST system is implemented
using STUMPS (Self-Test Using MISR and PRPG) architecture. A typical LBIST
system is as shown in the figure below:
 |
Figure
1: A typical LBIST system
|
Components of an LBIST system: A typical LBIST
system comprises following:
- Logic to be tested, or, as is called Circuit Under Test (CUT): In case of LBIST, the logic to be tested through LBIST is the Circuit under Test (CUT). Any random logic residing on the chip can be brought under LBIST following a certain procedure.
- PRPG (Pseudo-Random Pattern Generator): A PRPG generates input patterns that are applied to internal scan chains of the CUT for LBIST testing. In other words, PRPG acts as a Test Pattern Generator (TPG) for LBIST. A PRPG can either use a counter or an LFSR for pattern generation.
- MISR (Multi-Input Signature Register): MISR obtains the response of the device to the test patterns applied. An incorrect MISR output indicates a defect in the CUT. In classical language, MISR acts as a ORA (Output Response Analyzer) for LBIST testing.
- A master (LBIST controller): The controller controls the functioning of the LBIST; i.e. clocks propagation, initialization and scan patterns flow in and out of the LBIST scan chains.
One of the most
stringent requirements in LBIST testing is the prohibition of X-sources. There
cannot be any source of ‘X’ during LBIST testing. By ‘X’, is meant a definite,
but unknown value. It might be either ‘0’ or ‘1’, but it is not known what
value is being propagated. All X-sources are masked and a known value is
allowed to be propagated in LBIST.
Why ‘X’ is prohibited in LBIST: As
stated above, there cannot be any ‘X’ propagating during LBIST testing. The
reason behind this is that LBIST involves MISR to calculate the signature of
the LBIST patterns. Since, the resulting signal is unique, any unknown value
can result in the corruption of the signature. So, there cannot be any ‘X’ in
LBIST testing.
Advantages of LBIST: As stated
above, there are many unique advantages of LBIST that make it desirable,
especially in safety critical designs such as those used in automobiles and
aeroplanes. LBIST offers many advantages as listed below:
- LBIST provides self-test capability to logic inside chip; thus, the chip can test itself without any external control and interference.
- This provides the ability to be tested at higher frequencies reducing test time considerably.
- LBIST can run while the chip is on field running functionally. Thus, it is very useful in safety critical applications wherein faults developed on field can be easily detectable at startup before chip goes into functional mode.
Overheads due to LBIST: Along
with many advantages, there are some overheads due to LBIST as mentioned below:
(i)
The LBIST implementation involves some hardware
on-chip to control LBIST. So, there are area and power impacts due to these. In
other words, the cost of chip increases.
(ii)
Also, ‘X’-masking involves addition of extra
logic gates in already timing critical functional signals causing impact on
timing as well.
(iii)
Another disadvantage of using LBIST is that even
the on-chip test equipment may fail. This is not the problem with testing using
outside equipment with proven test circuitry
References:
- Identification and reduction of safe-stating points in LBIST designs
- Logic built-in self-test
- Challenges in LBIST verification of high reliability SoCs
Also read:
Scan chains – the backbone of DFT
What are scan
chains: Scan chains are the elements in scan-based designs that are used
to shift-in and shift-out test data. A scan chain is formed by a number of
flops connected back to back in a chain with the output of one flop connected
to another. The input of first flop is connected to the input pin of the chip
(called scan-in) from where scan data is fed. The output of the last flop is
connected to the output pin of the chip (called scan-out) which is used to take
the shifted data out. The figure below shows a scan chain.
 |
| A scan chain |
Purpose of scan
chains: As said above, scan chains are inserted into designs to shift
the test data into the chip and out of the chip. This is done in order to make
every point in the chip controllable and observable as discussed below.
How normal flop is
transformed into a scan flop: The flops in the design have to be
modified in order to be put in the scan chains. To do so, the normal input (D)
of the flip-flop has to be multiplexed with the scan input. A signal called
scan-enable is used to control which input will propagate to the output.
 |
| Figure showing transition of a normal flop to scan flop |
If scan-enable = 0,
data at D pin of the flop will propagate to Q at the next active edge
If scan-enable= 1,
data present at scan-in input will propagate to Q at the next active edge
Scan terminology:
Before we talk further, it will be useful to know some signals used in scan
chains which are as follows:
- Scan-in: Input to the flop/scan-chain that is used to provide scan data into it
- Scan-out: Output from flop/scan-chain that provides the scanned data to the next flop/output
- Scan-enable: Input to the flop that controls whether scan_in data or functional
data will propagate to outputPurpose of testing using scan: Scan testing is carried out for various reasons, two most prominent of them are:
- To test stuck-at faults in manufactured devices
- To test the paths in the manufactured devices for delay; i.e. to test whether each path is working at functional frequency or not
How a scan chain
functions: The fundamental goal of scan chains is to make each node in
the circuit controllable and observable through limited number of patterns by
providing a bypass path to each flip-flop. Basically, it follows these steps:
- Assert scan_enable (make it high) so as to enable (SI -> Q) path for each flop
- Keep shifting in the scan data until the intended values at intended nodes are reached
- De-assert scan_enable (for one pulse of clock in case of stuck-at testing and two or more cycles in case of transition testing) to enable D->Q path so that the combinational cloud output can be captured at the next clock edge.
- Again assert scan_enable and shift out the data through scan_out
How Chain length is
decided: By chain length, we mean the number of flip-flops in a single
scan chain. Larger the chain length, more the number of cycles required to
shift the data in and out. However, considering the number of flops remains
same, smaller chain length means more number of input/output ports is needed as
scan_in and scan_out ports. As
Number of ports
required = 2 X Number of scan chains
Since for each scan chain, scan_in and scan_out port is needed.
Also,
Number of cycles
required to run a pattern = Length of largest scan chain in design
Suppose, there are 10000 flops in the design and there are 6
ports available as input/output. This means we can make (6/2=) 3 chains. If we
make scan chains of 9000, 100 and 900 flops, it will be inefficient as 9000
cycles will be required to shift the data in and out. We need to distribute
flops in scan chains almost equally. If we make chain lengths as 3300, 3400 and
3300, the number of cycles required is 3400.
Keeping almost equal number of flops in each scan chain is referred to as chain balancing.
Also read:
- MBIST (Memory Built-In Self-Test)
- Lockup latch - Principle and application
- Controllability and observability - basics of DFT
- LBIST
- How propagation of 'X' happens through different logic gates
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