Can a net have negative propagation delay?

As we discussed in ‘’Is it possible for a logic gate to have negative propagation delay”, a logic cell can have negative propagation delay. However, the only condition we mentioned was that the transition at the output pin should be improved drastically so that 50% level at output is reached before 50% level of input waveform.

In other words, the only condition for negative delay is to have improvement in slew. As we know, a net has only passive parasitic in the form of parasitic resistances and capacitances. Passive elements can only degrade the transition as they cannot provide energy (assuming no crosstalk); rather can only dissipate it. In other words, it is not possible for a net to have negative propagation delay.

However, we can have negative delay for a net, if there is crosstalk, as crosstalk can improve the transition on a net. In other words, in the presence of crosstalk, we can have 50% level at output reached before 50% level at input; hence, negative propagation delay of a net.

Also read:

• Bubble errors and bubble error correction
• Noise margins
• Can hold be frequency dependant
• Worst slew propagation
• Latchup in CMOS devices

Temperature inversion – concept and phenomenon

To understand the phenomenon of temperature inversion, let us first understand the concepts governing the conductivity of semiconductor devices with respect to changes in temperature.

Phenomenon governing semoconductor conductivity vs. temperature: In all, there are two phenomenon that govern the conductivity in any device-

• Carrier concentration: Electrons and holes are the charge carriers in a semiconductor. More is the number of carriers; greater is the conductivity of the material. Rise in temperature causes greater number of bonds to break due to higher number of collisions among vibrating molecules; thus, resulting in higher number of carriers with increase in temperature. This factor tends to increase the conductivity with increasing temperature. More the number of carriers, greater is the conductivity.
• Mobility of the carriers: Mobility is another measure of conductivity. Greater is the mobility of carriers, carriers move with greater speed, thus, contributing more to the overall current; hence, greater is the conductivity of the material. With increase in temperature, lattice vibrations increase resulting in less mobility of free carriers. So, this factor tends to decrease the conductivity with temperature increase.

Summing up, the trend of conductivity with temperature depends upon which of the above two factors dominates. Based upon the conductivity, the materials can be divided into three types - conductors, insulators and semi-conductors. Let us explore how the conductivity of these materials is based on the above two factors:

Conductivity of conductors (metals): Metals have abundance of loosely attached nearly free electrons (as is commonly called, the electron sea), the carriers of electric current. The increase in carrier concentration is ignorable with change in temperature. So, mobility factor dominates. The conductivity of conductors decreases with increase in temperature.

Conductivity of insulators (non-metals): Insulators have almost negligible free carriers. The electrons in insulators are tightly bound to atoms by bonds. The conductivity is negligible in insulators due to limited number of carriers. However, the number of free carriers increases exponentially with temperature. This increase in carrier concentration with temperature outpaces the decrease in mobility thereby making the insulators to gain conductivity with rise in temperature. So, the conductivity in insulators increases with rise in temperature.

Conductivity trend in Semiconductors: Semiconductors have conductivity in-between metals and insulators. These are the class of insulating materials in which electrons are loosely bound to atoms. A small energy is needed to break these bonds and supply free carriers, which can be supplied by potential difference applied across the semiconductor, or, by temperature itself, in the form of thermal energy. So, there can be any of the two factors dominating depending upon the voltage applied across the semiconductor. The decrease or increase in conductivity of semiconductor depends upon which of the two factors dominates. For CMOS transistors, the number of charge carriers directly translates to threshold voltage.

At high voltage levels applied, there is abundance of free charge carriers as a result of the energy supplied by the potential difference created. At this state, there is not significant change in carrier concentration with increase in temperature; so, the mobility factor dominates; thereby, decreasing the conductivity with temperature. In other words, at high levels of voltages applied, the conductivity of semiconductors decreases with temperature.

Similarly, in the absence of any voltage applied, or with little voltage applied, the semiconductor behaves similar to an insulator with very less number of carriers, those resulting from only thermal energy. So, increase in carrier concentration is the dominating factor. So, we can say that at low applied voltages, the conductivity of semiconductors increases with temperature.

The concept of temperature inversion: With reference to the discussion we had earlier, at higher technology nodes, the voltage levels used to be high. So, traditionally, the delay of CMOS logic circuits used to increase with temperature. So, the most timing critical corner used to be worst process, minimum voltage and maximum temperature. However, with scaling down of technology, the voltage levels have also scaled down. Due to this, at sub-nanometer technology levels, both the factors come into play. At lower range of the operating voltage levels, first factor comes into play. In other words, at lower technology nodes, the most setup timing critical corner has become worst process, minimum voltage and minimum temperature. This shift in setup critical corner, in VLSI jargon, is termed as temperature inversion.

Also read:

• Interesting design quiz : BCD multiply by 5 circuit
• Latchup in CMOS design
• Our world - digital or analog
• Power aware RTL design
• Race conditions

Can hold check be frequency dependant?

We often encounter people argue that hold check is frequency independent. However, it is only partially true. This condition is true only for zero-cycle hold checks. By zero cycle hold checks, we mean that the hold check is performed on the same edge at which it is launched. This is true in case of timing paths between same polarity registers; e.g. between positive edge-triggered flops. Figure 1 below shows timing checks for a data-path launched from a positive edge-triggered flip-flop and captured at a positive edge-triggered flip-flop. The hold timing, in this case, is checked at the same edge at which data is launched. Changing the clock frequency will not cause hold check to change.

Figure 1: Setup and hold checks for positive edge-triggered to positive edge-triggered flip-flop

Most of the cases in today’s designs are of this type only. The exceptions to zero cycle hold check are not too many. There are hold checks for previous edge also. However, these are very relaxed as compared to zero cycle hold check. Hence, are not mentioned. Also, hold checks on next edge are impossible to be met considering cross-corner delay variations. So, seldom do we hear that hold check is frequency dependant. Let us talk of different scenarios of frequency dependant hold checks:

1.  From positive edge-triggered flip-flop to negative edge-triggered flip-flop and vice-versa: Figure 2 below shows the setup and hold checks for a timing path from positive edge-triggered flip-flop to a negative edge-triggered flip-flop. Change in frequency will change the distance between the two adjacent edges; hence, hold check will change. The equation for hold timing will be given for below case as:

T_data + T_clk/2 > T_skew + T_hold

or

Tslack =  T_clk/2 - T_hold - T_skew + T_data

          Thus, clock period comes into picture in calculation of hold timing slack.

Figure 2: Setup and hold checks for timing path from positive edge-triggered flip-flop to negative edge-triggered flip-flop

Similarly, for timing paths launching from negative edge-triggered flip-flop and being captured at positive edge-triggered flip-flop, clock period comes into picture. However, this check is very relaxed most of the times. It is evident from above equation that for hold slack to be negative, the skew between launch and capture clocks should be greater than half clock cycle which is very rare scenario to occur. Even at 2 GHz frequency (T_clk = 500 ps), skew has to be greater than 250 ps which is still very rare.

Coming to latches, hold check from a positive level-sensitive latch to negative edge-triggered flip-flop is half cycle. Similarly, hold check from a negative level-sensitive latch to positive edge-triggered flip-flop is half cycle. Hence, hold check in both of these cases is frequency dependant.

2. Clock gating hold checks: When data launched from a negative edge-triggered flip-flop gates a clock on an OR gate, hold is checked on next positive edge to the edge at which data is launched as shown in figure 3, which is frequency dependant.

Figure 3: Clock gating hold check between data launched from a negative edge-triggered flip-flop and and clock at an OR gate

           Similarly, data launched from positive edge-triggered and gating clock on an AND gate form half cycle hold. However, this kind of check is not possible to meet under normal scenarios considering cross-corner variations.

3)      Non-default hold checks: Sometimes, due to architectural requirements (e.g. multi-cycle paths for hold), hold check is non-zero cycle even for positive edge-triggered to positive edge-triggered paths as shown in figure 4 below.

Figure 4: Non-default hold check with multi-cycle path of 1 cycle specified

Also read:

• Lockup latch - principle, application and timing
• Data checks - all about data setup and data hold checks
• Worst slew propagation
• On-chip variations - the STA takeaway