Setup time vs hold time

In digital designs, each and every sequential element has some restrictions related to the data with respect to clock in the form of windows in which data can change or not. There is always a region around the active edge of the clock in which data is not allowed to change at the input of the sequential element. This is because, if the data changes at the input within this window, we cannot guarantee the output. If this happens, there can be one of the three possibilities:

• Current output data can be the result of current input data
• Current output data can be the result of previous input data
• The output can go metastable (as explained in metastability)

This region around clock edge is marked by two boundary lines, one perrtaining to setup time, and other to hold time. The region between these two lines is generally termed as setup-hold window. Figure 1 below shows the setup-hold window.

Figure 1: Figure showing setup/hold window of a sequential element

There are certain points of difference between setup time and hold time that we need to keep in mind:

• Setup time signifies the point in time before which data needs to be stable, whereas hold time is the point of time after which the data needs to be stable

• Adherence to setup time ensures that the data launched at previous active clock edge by another flip-flop gets captured at the current clock edge. On the other hand, adherence to hold time ensures that the data launched at the current edge does not get captured on the same edge.

• Above point also means that setup time adherence ensures that the design goes to next state smoothly, whereas hold time adherence means the current state is not disturbed.

Hope this post helped you in understanding the basic difference in setup time and hold time.

Also read:

• Clock latency
• False paths basics and examples
• Propagation delay in logic gates
• Integrated clock gating cell (ICG)
• Basics of latch timing

Propagation delay of a net

Definition of net propagation delay: The propagation delay of a net can be defined as the amount of time it takes a logic signal to propagate from the output of one logic gate to the input of another. Normally, it is defined as the difference between the times when the output of driver gate of net reaches 50% of its final value to when the input of the load cell of net reaches 50% of its final value.

How net delay is calculated: The net delay is calculated from the parasitics of the net. The parasitics are calculated based upon the topology of the net. These may also be read in from the parasitics file (SPEF, DSPF etc). The resulting RC-circuit resulting from the net topology is, then, simulated using certain algorithms (cosidering speed and accuracy requirements) for net delay.

Hold time

Definition of hold time: Hold time is defined as the minimum amount of time after arrival of clock's active edge so that it can be latched properly. In other words, each flip-flop (or any sequential element, in general) needs data to be stable for some time after arrival of clock edge such that it can reliably capture the data. This amount of time is known as hold time.

We can also link hold time with state transitions. We know that the data to be captured at the current clock edge was launched at previous clock edge by some other flip-flop. And the data launched at the current clock edge must be captured at the next edge. Adherence to hold time ensures that the data launched at current edge is not captured at the current clock edge. And the data launched at previous edge is captured and not disturbed by the one launched at current edge. In other words, hold time ensures that the current state of the design is not disturbed.

Figure 1 : Hold time

Figure 1 shows that data is allowed to toggle after the yellow dotted line. This yellow dotted line corresponds to hold time. The time difference between the active clock edge and this yellow dotted line is hold time. Data cannot toggle before this yellow dotted line for a duration known as setup-hold window. Occurrence of such an event is termed as hold violation. The consequence of such a violation can be capture of wrong data (better termed as hold check violation) or the sequential element going into meta-stable state (hold time violation).

Figure 2: A positive level-sensitive D-latch

Latch hold time: Figure 2 shows a positive level-sensitive latch. If there is a toggling of data at the latch input close to negative edge (while the latch is closing), there will be an uncertainty as if data will be capture reliably or not. For data to be captured reliably, next data must not reach Node C when closing edge of clock arrives at the input transmission gate. For this to happen, data must not travel NodeA -> NodeB -> NodeC before clock edge arrives. Data must change after this time interval only. 

Flip-flop hold time: Figure 3 below shows a master-slave negative edge-triggered D flip-flop using transmission gate latches. This is the most popular configuration of a flip-flop used in today's designs. Let us get into the details of hold time for this flip-flop. For this flip-flop to capture data reliably, new data must not be present at nodeD at the arrival of negative edge of clock. So, data must not travel NodeA -> NodeB -> NodeC -> NodeD when clock edge arrives. For data to not reach NodeD when clock edge arrives, it must toggle after some interval A with respect to clock. This interval corresponds to hold time of the flip-flop.We can also say that the hold time of flip-flop is, in a way, hold time of master latch.

Figure 3: D-flip flop

Hope this helped you in understanding the basics of hold time. You can suggest any improvement you think below in comments.

Setup and hold interview questions

Almost every interview for a VLSI design engineer has at least a question related to setup and hold. So, it is very important to prepare well. We list below a few topics related to setup and hold that may prove to be more than useful for setup and hold related interview questions.

• Setup time

• Positive, negative and zero setup time

• Hold time

• Positive, negative and zero hold time

• STA problem : hold time manipulation

• Setup time vs hold time

• Setup checks and hold checks

• Can hold check be frequency dependent?

• What makes a timing path both setup and hold timing critical

• Setup and hold violations

• How to fix setup violations

• How to fix hold violations

• How multicycle paths manipulate setup and hold checks

• Setup and hold times for latches

• Concept of time borrowing in latches

• STA problem: what is the maximum frequency following circuit can work at?

• STA problem: can you figure out if there is any setup/hold violation in the circuit?

• STA problem : Modeling skew requirements with the help of data-to-data checks

• Data checks - all about data setup and data hold check

• Clock gating checks

• Clock gating checks at a multiplexer

Please share your interview experiences with us in comments so that these can be of help to other readers. Also, if you have any suggestion for us, you can get in touch with us. All the best. :-)

Liberty format : an introduction

What is liberty format: Liberty format is an industry standard format used to describe library cells of a particular technology. A cell could be a standard cell, IO Buffer, complex IP etc. Library cell description contains a lot of information like timing information, power estimation, other several attributes like area, functionality, operating condition etc. Speaking more technically, liberty format is a format to represent timing and power properties of black boxes (which we cant descend into). Liberty is an ASCII format, usually represented in a text file with extension ".lib". In this section, we will discuss timing aspects (delay and transition times) related to liberty format.

How is liberty file populated with data: The cells represented through liberty files are first simulated under a variety of conditions representative of actual design conditions that the cell may be exposed to. This process is known as characterization of library cells. As a very simple example, the delay of an inverter depends upon the input transition time and output load capacitance seen by it. The inverter will be characterized for a range of input transitions and output load capacitances. This characterization data, will then, be put into liberty in the form of a look-up table representing delay values at different transition times and load values.

To understand the different constructs related to timing in liberty file, let us take example of inverter. Rising transition at the input of inverter produces falling transition at the output of inverter and vice-versa. Hence there are two types of delay :

1. Rise delay : It is the propagation delay (see definition) between output and input when output changes from 0 to 1.
2. Output fall delay : It is the propagation delay between output and input when output is changing from 1 to 0.

In the real world, signal does not change its state from 0 to 1 or 1 to 0 abruptly. It takes some time to change its state. Hence, delay is measured based upon the threshold points. Threshold points in the liberty file are specified as below:

# threshold point of input falling edge
input_threshold_pct_fall : 50.0 ;

# threshold point of input rising edge
input_threshold_pct_rise : 50.0 ;

#threshold point of output falling edge
output_threshold_pct_fall : 50.0 ;

#threshold point of output rising edge
output_threshold_pct_rise : 50.0 ;

NOTE : these values are in percentage. e.g. If vdd is 5v then all of the above values will be 2.5.

So, Output rise delay is time difference between output_threshold_pct_rise and input_threshold_pct fall. Similarly Output fall delay is time difference between output_threshold_pct_fall and input_threshold_pct_rise.

Transition time : Time it takes for a signal to changes its state from one level to another level. Transition time is represented in terms of slew in liberty. Actually slew is inversely proportional to transition time. More the transition time, lesser is the slew rate and vice-versa. As we know that

voltage transition at the output is :

V = Vdd * [ 1 - e^ ( -t/(RC ) ) ] 

As Voltage equation is exponential, the voltage waveform is asymptotic at ends It is difficult to determine the exact start and end point of transition hence transition time is defined in terms of threshold values as follow :

# lower threshold point for falling  edge

slew_lower_threshold_pct_fall  : 30;

# upper threshold point for falling  edge

slew_upper_threshold_pct_fall : 30;

# lower threshold point for rising  edge

slew_lower_threshold_pct_rise : 70;

# upper threshold point for rising  edge

slew_upper_threshold_pct_rise : 70;

Reading from a file in tcl

It is very common to read from and/or write to a file in any programming language. In tcl also, one frequently uses file operations. read command in tcl reads the entire file and stores it into a variable. One can, then, perform the desired operations onto the read data. The normal command sequence to read a file in tcl language is as below:

// script to read and display contents

set infile [open input_file.rpt r] // Create a file pointer and point it to the file to be read

set file_data [read $infile]            // Assign file_data with contents of infile

close $infile                                        // Detach the file pointer from file to be read

set lines [split $file_data “\n”]   

// Split the file contents by lines and assign each line to an element of list

foreach element $lines {

                puts $element                  // Display each element of $lines onto screen.

}

2-input AND gate using 2:1 mux

2-input AND gate implementation using 2:1 mux: Figure 1 below shows the truth table of a 2-input AND gate. If we observe carefully, OUT equals '0' when A is '0'. And OUT follows B when A is '1'. So, if we connect A to the select pin of a 2:1 mux, AND gate will be implemented if we connect D0 to '0' and D1 to 'B'.

Figure 1: Truth table of AND gate

Figure 2 below shows the implementation of 2-input AND gate using a 2:1 multiplexer.

Figure 2: Implementation of AND gate using a 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux: Figure 3 below shows the truth table of a 2-input NAND gate. If we observe carefully, OUT equals '1' when A is '0'. Similarly, when A is '1', OUT is B'. So, if we connect SEL pin of mux to A, D0 pin of mux to '1' and D1 to B', then it will act as a NAND gate.

Figure 3: Truth table of 2-input NAND gate

Figure 4 below shows the implementation of a 2-input NAND gate using 2:1 mux.

Figure 4: Implementation of 2-input NAND gate using 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input AND gate using 2:1 mux

2-input OR gate using 2:1 mux

2-input OR gate using 2x1 mux: Figure 5 below shows the truth table for a 2-input OR gate. If we observe carefully, OUT equals B when A is '0'. Similarly, OUT is '1' (or A), when A is '1'. So, we can make a 2:1 mux act like a 2-input OR gate, if we connect D0 pin to B and D1 pin to A, with select connected to A.

Figure 5: Truth table of 2-input OR gate

Figure 6 below shows the implementation of 2-input OR gate using a 2:1 multilpexer:

Figure 6: Implementation of 2-input OR gate using 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux

2-input XNOR gate using 2:1 mux

2-input XNOR gate using 2x1 mux: Figure 1 below shows the truth table of a 2-input XNOR gate. If we observe carefully, OUT equals B' when A is '0' and equals B when A is '1'. So, a 2-input XNOR gate can be implemented from a 2x1 mux, if we connect SEL pin to A, D0 to B' and D1 to B.

Figure 1: Truth table of 2-input XNOR gate

The implementation of 2-input XOR gate using a 2x1 mux is as shown in figure 2.

Figure 2: Implementation of 2-input XNOR gate using 2x1 mux

Similarly, we can observe the output for different values of B and follow the same steps to obtain the XNOR gate implementation.

8x1 multiplexer using 4x1 multiplexer

An 8x1 mux can be implemented using two 4x1 muxes and one 2x1 mux. 4 of the inputs can first be decoded using each 4-input mux using two least significant select lines (S0 and S1). The output of the two 4x1 muxes can be further multiplexed with the help of MSB of select lines at further stage. The implementation of 8x1 using 4x1 and 2x1 muxes is shown in figure 1 below:

2-input NOR gate using 2:1 mux

2-input NOR gate using 2x1 mux: Figure 1 below shows the truth table of a 2-input NOR gate. If we observe carefully, OUT equal B' when A is '0'. Similarly, OUT equals '0' when A is '1'. So, we can make a 2-input mux act like a 2-input NOR gate, if we connect SEL of mux to A, D0 to B' and D1 to '0'.

Figure 1: Truth table of 2-input NOR gate

Figure 2 shows the implementation of 2-input NOR gate using 2:1 mux.

Figure 2: Implementation of 2-input NOR gate using 2x1 mux

Similarly, we can connect B to select pin of mux and follow the same procedure of observation from truth table to get the NOR gate implemented.

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux

Matchstick game bonanza!!

Problem: There are 'N' matchsticks placed on the table. You and your opponent are to pick any number of matchsticks between 1 and 5. Its your turn first. The one picking the last stick loses the game. You have to device a strategy such that you always win the game.Also, is there any starting number that cannot guarantee that you always win?

Solution: Here, you have to ensure that the control of the game always remains in your hands. Let us approach this problem from the last. The last matchstick has to be picked by your opponent so as to ensure your win. So, your last turn must ensure that there must be only one matchstick left on the table. If this is not the case, say there are 2 matchsticks. Then, your opponent will pick 1 stick and you are left with only one stick to pick and lose the game.

Similarly, one turn before last of your opponent, there must be more than 6 sticks so that he cannot leave you with 1 stick by picking 5 of them. But if there are more than 7 sticks, he may leave you with the same situation by leaving 7 on the table. If you leave 7, the other can at max pick 5 and min 1 leaving any number between 6 and 2 on the table. You can now pick the desired number leaving the last stick to be picked by him. Now, if there were 8 sticks on the table, your opponent would pick 1 leaving you with 7 sticks. :-( Similarly, one turn before, you should have left 13 sticks on the table.

So, your approach should be to leave (6M + 1) sticks on the table always. Ensure that at the end of each round, 6 less matchsticks are there on the table. (For instance, if your opponent picks 3 sticks, you also pick 3).

But there is a catch in this game, if there are already (6M + 1) sticks on the table initially, and its your turn first, you cannot ensure after your first turn the winning strategy. Now, the control goes into the hand of your opponent and you are at the verge of losing the game.

Similarly, 5 can be replaced with any number 'K'. At the end of each turn, you have to ensure there are (K+1)M + 1 sticks left on the table.

2-input XOR gate using 2:1 mux

2-input XOR gate using 2x1 mux: Figure 1 shows the truth table for a 2-input XOR gate where A and B are the two inputs and OUT is equal to XOR of A and B. If we observe carefully, OUT equals B when A is '0' and B' when A is '1'. So, a 2:1 mux can be used to implement 2-input XOR gate if we connect SEL to A, D0 to B and D1 to B'.

Figure 1: Truth table of 2-input XOR gate

Figure 2 shows the implementation of 2-input XOR gate using 2x1 mux.

Figure 2: Implementation of 2-input XOR gate using 2x1 mux

Similarly, we can connect B to select of mux, and get the XOR gate implemented using similar procedure.

Also read:

• NOT gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux

NOT gate using 2:1 mux

NOT gate using 2:1 mux: Figure 13 shows the truth table for a NOT gate. The only inverting path in a multiplexer is from select to output. To implement NOT gate with the help of a mux, we just need to enable this inverting path. This will happen if we connect D0 to '1' and D1 to '0'.

Figure 1: Truth table of NOT gate

We can also say that we need to propagate '0' to output when input (select) is 1 and '1' when input is '0'. Figure 14 shows the implementation of NOT gate using 2x1 mux:

Figure 2: NOT gate implementation using 2:1 mux

Also read:

• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux

Zero cycle paths

Zero cycle path: A zero cycle timing path is a representative of race condition between data and clock. A zero cycle path is one in which data is launched and captured on the same edge of the clock. In other words, setup check for a zero cycle path is zero cycle, i.e., it is on the same edge as the one launching data. Hold check, then, will be one cycle before the edge at which data is launched. Figure 1 below shows the setup check and hold check for a zero cycle timing path.

Figure 1: Setup check and hold check for zero cycle paths

How to specify zero cycle path: As we know, by default, setup check is single cycle (is checked on the next edge with respect to the one on which data is launched). If the FSM requires a timing path to be zero cycle, it has to be specified using the SDC command "set_multicycle_path".

Figure 2: Default setup and hold checks for single cycle timing path

The default setup and hold check for same edge timing paths is single cycle and zero cycle as shown in figure 2 above. To model it as a zero cycle path (as in figure 1), we need to apply following timing constraint:

set_multicycle_path 0 -setup -from <startpoint> -to <endpoint>

where <startpoint> is the the flip-flop which launches the data and <endpoint> is the flip-flop which captures the data. In other words, as viewed from application perspective, zero cycle path is one of the special cases of a multi-cycle path only. Above multicycle constraint modifies the setup check to be zero cycle. Hold check also, shifts one edge back.

Also read:

• Multicycle paths - the architectural perspective
• Multicycle paths handling in STA
• Data checks - all about data setup and data hold checks
• Race conditions in digital circuits
• Clock gating checks