Recovery and removal checks

Recovery and removal checks are associated with deassertion of asynchronous reset. The assertion of reset causes the output to get reset and deassertion transfers the control of output to clock signal; i.e., deassertion of reset does not change the output as we discussed in post synchronous and asynchronous resets. However, to ensure that the design comes out of reset in deterministic cycle and to avoid metastability, there must be a region around arrival of clock edge within which reset must not be deasserted. This is similar to setup and hold timing checks, the difference being that:
Setup and hold checks are associated with synchronous data signals for a flop and are applied to both rise and fall transitions of data. Recovery and removal checks, on the other hand, are for asynchronous reset transitioning from active state to inactive state only (deassertion of reset).
To properly understand what recovery and removal checks are, we need to understand what asynchronous reset assertion and deassertion does.

Asynchronous reset assertion: In a flip-flop, assertion of reset causes the output to go to its reset value (which is normally "0"). The assertion of reset is an asynchronous event and is not impacted by the state of clock. Figure 1 below depicts the assertion of reset. As it can be seen, Output asynchronously goes to "0" as an effect of reset going to its active state "1".


Asynchronous reset deassertion: The deassertion of asynchronous reset causes the output to get out of the impact of reset and behave like a normal flip-flop. When the reset gets deasserted, its output remains to be "0" until the clock edge. When the clock edge arrives, the value at the input of the flop propagates to the output. Figure 2 below depicts the same. However, the position of reset deassertion with respect to clock edge matters here as is the case with setup and hold checks. If the reset toggles in the vicinity of clock edge, the flip-flop may go metastable. This is avoided by defining recovery and removal checks for reset deassertion. For the sake of simplicity, we can say that recovery and removal checks are setup and hold checks for reset deassertion.



Reset recovery check: Recovery check ensures that the deasserted reset signal allows the clock signal to take control of the output at the desired clock edge. For this, reset signal must be stable at least "recovery time" before the active clock edge. Recovery time is the minimum time required between the deassertion of reset signal and arrival of clock edge. This can be modelled similarly as a setup check with the difference of it being a single sided synchronous check only.

Reset removal check: Removal check ensures that the deasserted reset signal does not get captured on the clock edge at which it is launched by reset synchronizer. For this, reset signal must be stable at lease "removal time" after the active clock edge. Removal time is the minimum time required after the arrival of clock edge for which reset must not be deasserted at the flop's reset pin. This can be modelled similarly as a hold check with the difference of it being a single sisded synchronous check only.

Figure below shows reset de-assertion as a complete picture and summarises what we have discussed in this post.



Next read: Reset basics

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9 comments:

  1. Hello Sir, It's an excellent explanation for the concept. I have a doubt. What if Reset Assertion occurs within either the Reset Recovery time or the removal time?

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    1. Hi

      Reset assertion can occur at any time, there is no relation of reset assertion to either recovery or removal times.

      However, if the same question is asked for reset deassertion, then the same thing will happen as what happens when data toggles between setup and hold time window. The flip-flop can either respond to reset deassertion at current edge, or may not respond. Furthermore, there is a possibility that it can go to metastable state.

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  2. Dear sir, thank you for the simplified and yet effective explanation. Sir,what is the underlying physics that's responsible for the existence of recovery and removal time?

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    1. Hi

      In my opinion, this is the simplest explanation. A flip-flop will need some time to change its state on the arrival of clock edge, so data must not change during this window. The position of left edge of this boundary with respect to clock edge is called setup time (recovery time in case of reset signal) and the right edge's position with respect to clock edge is called hold time (removal time in case of reset signal). And the window during which the signal is not allowed to toggle is called setup-hold window.

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  3. In many systems resets come from IOs and they are in form of a pulse.
    For an active high async reset , the pulse may go low any time.
    How is this ensured that reset is not released in recovery of removal time shown in the waveform/figure ?
    Thanks for such a great post !

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    1. Hi

      Nice question, in such cases you use a reset synchronizer. It is a special kind of synchronizer which synchronizes only the deassertion of reset.

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    2. Question on this special reset synchronizer. How does it ensure that the reset to this reset-synchronizer comes at right time and does not cause the synchronizer to go into metastability

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    3. Hi

      Reset synchronizer is designed not to avoid metastability.

      It is designed to absorb metastability such that it does not propagate to the flops in the fanout of reset synchronizer.

      Reset synchronizer consists of at least two flops is series. (assuming 2 stages), The first stage is allowed to go metastable with the confidence that most of the times its metastability will be resolved in one cycle. Thus, the metastability will not propagate to the 2nd stage with very high probability. In this way, reset synchronizer (or any other synchronizer) absorbs metastability.

      In case the probability of propagation of metastability to stage 2 is high, we can use 3-stage reset synchronizer and so on.

      I hope it helped you clear your understanding. Please feel free to ask in case of any queries.

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  4. "Removal time is the minimum time required between the arrival of clock edge and the deassertion of reset."
    sorry sir, but this sentence is confusing, "between the arrival of clock edge and the deassertion of reset" I suppose this described "recovery time"

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