Clock gating checks in case of mux select transition when both clocks are running

PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. What are the architectural and STA considerations for the same?

SOLUTION:
This is a very good example to understand how clock gating checks work, although you may/may not find any practical application for the same. We have to toggle the select of the multiplexer such that there is no glitch at the output. Let us consider architectural considerations first:

Architectural considerations:

Launching flip-flop of 'select' signal: In the post clock gating checks at a multiplexer, we discussed that if there is a mux getting clock at its inputs and select as data, then, there are two possible scenarios:

  • If the other clock is at state "0", then AND type check is formed and select has to launch from negative edge-triggered flip-flop
  • If the other clock is at state "1", then OR type check is formed and select has to launch from positive edge-triggered flip-flop
Now, since both the clocks are running simultaneously, both with act as "other clock" for each other. Let us choose to keep both the clocks at state "0" when select toggles. The same discussion holds true for the other scenario as well, just that appropriate values will hold. Thus,

(i) Both clocks required to be at state '0' when clock toggles
(ii) There is AND-type clock gating check formed between 'select' and both clocks 
(iii) 'select' launches from negative edge-triggered flip-flop.


Valid negative edges when 'select' can toggle: Now, as mentioned above both the clocks should be zero when select toggles. Figure below shows the valid and invalid edges where 'select' can toggle. As it turns out, select can toggle only on edges labelled "VALID" as both "CLOCK" and "DIV_CLOCK" will be zero then.

 So, to ensure that "SEL" toggles only when DIV_CLOCK is "0", we can add logic to the input of the flip-flop launching "SEL" such that it allows to propagate "SEL" only when DIV_CLOCK is "0".


In the above diagram, flip-flop launching "SEL" will hold its value when DIV_CLOCK = 0. We have to keep in mind that this implementation is just a representation of what needs to be done. the actual implementation may be more complex than this depending upon the requirements.

Timing considerations: Now coming to the timing considerations, we need to ensure that the setup and hold conditions are met, which are as shown in the figure below:

Also read:




16 comments:

  1. Hi sir
    What will be the other input of mux i.e at 1 ?
    I think it is also a select.
    Does it correct or wrong

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    Replies
    1. Hi Kalyan

      Yes, the other input will act as "enable" for the clock coming at one input.

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    2. Hi sir,
      In the above figure we need to give enable at zero input of mux and select at one input of mux right?

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    3. Hi Kalyan

      No, that is not a compulsion. Theoretically, all the three inputs may get clock as well as data. But while calculating glitch probability at the output for one input as a clock, we will consider others as "enable" only. And vice-versa.

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    4. Sorry sir,
      I don't get your answer..
      Please explain in better way

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    5. This comment has been removed by the author.

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    6. Hi

      The basic fundamental is that we cant allow a glitch in clock path. This will happen only when select toggles either when both inputs are zero or when both inputs are one. While doing clock gating check analysis for one of the clocks, we need assume all the other inputs as data only. For example, for "CLOCK", to arrive at the type of clock gating check, we need to know the state of "DIV_CLOCK" when the select toggles. If it is 0, then clock gating check will be AND-type and vice-versa. Similar is the case for "DIV_CLOCK".

      Now, there are for possible cases for both the clocks, "00", "01", "10" and "11". Out of these, "00" and "11" satisfy our criteria. So, we can design accordingly.

      Let us say we design architecture such that select toggles only when the state is "00". This has been shown in this post too. So, we have to launch select from "negative edge of CLOCK", since we have to meet AND-type clock gating check with respect to both the clocks.

      I hope I was able to answer your query. We can discuss more in case any clarity needed.

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    7. To make select to toggle only when both clocks are zero we need to give enable at zero input of mux so that negative flop also launch data at neg edge..so that it satisfy and gating check...

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    8. In this case only and gating checks only happen....what about or gating checks

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    9. The basic idea is that there should not be any glitch at the output, which is taken care of in this example by toggling the select of mux when both clocks are zero, which forms AND check with both clocks. Another case could be toggling select when both clocks are 1, forming OR check. This would also make sense to prevent glitch at the output of the mux. It all depends upon what is the logic behind your RTL design implementation.

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  2. This comment has been removed by the author.

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  4. Hi sir,
    The clock for latch is also a 'CLOCK' i.e at input

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  5. Hello,
    you are saying:
    > In the above diagram, flip-flop launching "SEL" will hold its value when DIV_CLOCK = 0.
    But we want to CHANGE the value when DIV_CLOCK=0
    You need to connect the bottom flop output to the "1" input of the mux and not to "0"!
    Am I missing something?
    Best Regards,
    David

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  6. simple solution would be "and clk and divclk" and use as clock to a neg edge trigged flop which outputs select

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    Replies
    1. negedge of "AND of clk and divclk" is negedge of divclk, right?

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