Worst Slew Propagation

Worst slew propagation is a phenomenon in Static Timing Analysis. According to it, the worst of the slews at the input pin of a gate is propagated to its output. As we know, the output slew of a logic cell is a function of its input slew and output load. For a multi-input logic gate, the output slew should be different for the timing paths through its different input pins. However, this is not the case. This is due to the reason that to maintain a timing grapth, each node in the design can have only 1 slew. So, to cover the worst scenario for setup timing, the maximum slew at each output pin should be equal to that caused by the input pin having worst of the slews. The output slew calculated is on the basis of worst input slew, even if the timing path for which the output slew is being calculated is not through the input pin with worst slew. Similarly, the best of the slews is calculated based upon the effect of all the input pins for hold timing analysis. We can refer to it as best slew propagation.

Let us illustrate with the help of a 2-input AND gate. As shown in figure below, let the slews at the input pins be denoted as SLEW_A and SLEW_B and that at the output pin as SLEW_OUT. Now, as we know:

SLEW_OUT = func (SLEW_A) if A toggles leading to OUT toggling

And SLEW_OUT = func (SLEW_B) if B toggles leading to OUT toggling

However, even though the timing path as shown through A pin, the resultant slew at output SLEW_OUT will be calculated as:

SLEW_OUT         =  func (SLEW_A) if func(SLEW_A) > func(SLEW_B)

                                =  func (SLEW_B) if func(SLEW_B) > func(SLEW_A)

Figure 1: Figure showing worst slew propagation

One may feel this as an over-pessimism inserted by timing analysis tool. Path based timing analysis will not have worst slew propagation phenomenon as it calculates output slew for each timing path rather than one slew per node. 

Similarly, for performing timing analysis for hold violations, the best of the slews at inputs is propagated to the output as mentioned before also. 

Also read:

• Race conditions
• All about clock signals
• Propagation delay of logic gates
• Comparison between array, linked list and vector

Depletion MOSFET and negative logic. Why it is not possible?

As we know, depletion MOSFET conducts current even with gate and source at same voltage level. To cut-off the current in depletion MOSFET, a voltage has to be applied at gate so as to exhaust the already existing carriers inside the channel. On the other hand, enhancement type MOSFET is cut-off when gate and source are at same voltage.

Taking the example of NMOS, for a depletion MOS, with source and gate at same level, there is still a channel available, hence, it conducts electric current. To bring it to cut-off, a negative potential is needed to be applied at gate (considering source at ‘X’ potential). Thus, with source at ‘X’ potential and gate at ‘X’ potential, drain attains the potential of source. Since, to cut-off the device, gate has to be given a voltage less than ‘X’, so we can say “when Gate is 1 and source is 1, then drain is 1”.  On the other hand, when source is 1 and gate is 0, drain attains ‘high impedance’. The reverse is true for PMOS.

Similarly, with the same logic, for an enhancement NMOS, “When Gate is 1 and source is 0, drain attains 0 potential”; similarly, “When Gate is 0 and source is 0, drain is 0”. The reverse is true for PMOS.

Source voltage	Gate voltage	Drain voltage for enhancement NMOS	Drain voltage for enhancement PMOS	Drain voltage for depletion NMOS	Drain voltage for depletion PMOS
0	0	Z	Z	0	0
0	1	0	Z	0	Z
1	0	Z	1	Z	1
1	1	Z	Z	1	1

Thus, we can say that it is due to the inherent properties of NMOS and PMOS that that they cannot be used to create negative level logic.

Enhancement and depletion MOSFETs

A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a 4-terminal device with Source, Drain, Gate and Body as its terminals. It is used for amplification or switching of electronic signals and is the most common transistor in both digital and analog integrated circuits. The generic structure of a MOSFET is shown in figure 1. The source and drain terminals are separated by a channel. The conduction of the channel is determined by the carrier density in the channel which is a function of voltage applied at the gate terminal. The body terminal is normally connected to the source so as to allow only minimal leakage current to flow.

Figure 1: A MOSFET

MOSFETs are categorized into two categories based upon the nature of channel:

        1)      Enhancement mode MOSFETs: In an enhancement MOSFET, the channel is devoid of carriers. The channel has to be created by creating a suitable voltage difference between gate and source terminals. With gate and source at same potential, only minimal current flows. However, when a positive potential difference is applied which is greater than threshold voltage for the MOSFET, a channel is created. Thus, the current will now flow between source and drain if there is a potential difference between them. Figure 2 below shows how a channel is formed on applying a voltage between source and gate terminals.

Figure 2: Channel formation in Enhancement MOSFET

        2)      Depletion mode MOSFETs: In a depletion mode MOSFET, the channel is already present with the help of ion-implantation.  Even with gate and source at same voltage, it will conduct current. The channel has to be depleted by applying suitable potential.

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