Clock gating checks in case of mux select transition when both clocks are running

PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. What are the architectural and STA considerations for the same?

SOLUTION:
This is a very good example to understand how clock gating checks work, although you may/may not find any practical application for the same. We have to toggle the select of the multiplexer such that there is no glitch at the output. Let us consider architectural considerations first:

Architectural considerations:

Launching flip-flop of 'select' signal: In the post clock gating checks at a multiplexer, we discussed that if there is a mux getting clock at its inputs and select as data, then, there are two possible scenarios:

• If the other clock is at state "0", then AND type check is formed and select has to launch from negative edge-triggered flip-flop

• If the other clock is at state "1", then OR type check is formed and select has to launch from positive edge-triggered flip-flop

Now, since both the clocks are running simultaneously, both with act as "other clock" for each other. Let us choose to keep both the clocks at state "0" when select toggles. The same discussion holds true for the other scenario as well, just that appropriate values will hold. Thus,

(i) Both clocks required to be at state '0' when clock toggles

(ii) There is AND-type clock gating check formed between 'select' and both clocks 

(iii) 'select' launches from negative edge-triggered flip-flop.

Valid negative edges when 'select' can toggle: Now, as mentioned above both the clocks should be zero when select toggles. Figure below shows the valid and invalid edges where 'select' can toggle. As it turns out, select can toggle only on edges labelled "VALID" as both "CLOCK" and "DIV_CLOCK" will be zero then.

 So, to ensure that "SEL" toggles only when DIV_CLOCK is "0", we can add logic to the input of the flip-flop launching "SEL" such that it allows to propagate "SEL" only when DIV_CLOCK is "0".

In the above diagram, flip-flop launching "SEL" will hold its value when DIV_CLOCK = 0. We have to keep in mind that this implementation is just a representation of what needs to be done. the actual implementation may be more complex than this depending upon the requirements.

Timing considerations: Now coming to the timing considerations, we need to ensure that the setup and hold conditions are met, which are as shown in the figure below:

Also read:

• Clock gating interview questions

What is the difference between a normal buffer and clock buffer?

A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a repeater which repeats the signal it is receiving, just as there are repeaters in telephone signal transmission lines. You must have noticed that we have two kinds of buffers (or any logic gate) available in standard cell libraries as:

• Clock buffer: The clock buffers are designed specifically to have specific properties that are supposed to be good for clock distribution networks (clock trees). The specific properties that are required in an ideal clock tree buffer are given as below. However, it is not possible to attain these ideal properties for every buffer at every technology node. It may be only possible to get close to these properties.
• Equal rise and fall times
• Less delays
• Less delay variations with PVT and OCV

• Normal buffer/data buffer: For a data buffer, the above properties are usually less desired

Usually, we can say that following differences may exist between a clock buffer and a normal buffer:

• In SoCs, clock routing is done in higher metal layers as compared to signal routing. So, to provide easier access to clock pins from these layers, clock buffers may have pins in higher metal layers. That is, vias are provided in standard cell itself instead of necessitating on having in clock distribution network. For a data buffer, the pins are expected to be in lower layers only.
• Clock buffers are balanced. In other words, rise and fall times of clock buffers are nearly equal. The reason behind this is that if the clock buffers are not balanced, there will be duty cycle distortion in the clock tree, which can lead to pulse width violations as discussed in minimum pulse width violation example. On the other hand, data buffers can compromise with either of rise/fall times. In other words, they dont need to have PMOS/NMOS size to be 2:1; and hence, can be of smaller size as compared to clock buffers.
• Due to above reason, clock buffers consume more power as compared to normal buffers.
• Generally, you will find clock buffers with higher drive strength as compared to normal buffers. So that a clock buffer can drive long nets and can have higher fanouts. This helps clock buffers, and hence, clock trees to have less overall delays.

Read next: Clock skew

Can jitter in clock effect setup and hold violations?

First of all, we need to understand what is meant by jitter. In most simplistic language, jitter is the uncertainty of a clock source in production of clock edges. For example, if we say that there is a 100 MHz clock source. Ideally, it should produce a clock edge at 0 ns, 10 ns, 20 ns... So, if we say that there was a clock edge at time t = 30 ns, we should get the next clock edge at t = 40 ns. But this is hardly so; due to the uncertainty of getting a clock edge, we might get the next edge between 39.9 ns to 40.1 ns. So, we say that 0.1 ns is the jitter in the period of the clock. In reality, the definition of jitter is more complex. But, for our scope, this understanding is sufficient.

Let us consider a simple timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop.

Now, let us come to our discussion. First, let us discuss the effect of clock jitter on setup slack.

Effect of clock jitter on setup slack for single cycle paths: From our knowledge of STA basics, setup check formed, in this case, will be from edge 1 -> edge 3. Now, if we know that edge 1 arrived at 20 ns, then edge 3 may arrive at any time (20 ns + CLOCK_PERIOD + jitter) and (20 ns + CLOCK_PERIOD - jitter). So, to cover worst case timing scenario, we need to time as per (20 ns + CLOCK_PERIOD - jitter). So, effectively, we will get (CLOCK_PERIOD - jitter) as effective clock period.

In other words, jitter in clock period makes the setup timing more tight. Or it decreases setup slack for single cycle timing paths.


Effect of clock jitter on hold slack for single cycle paths: Going on the same grounds as setup slack, hold check will be from edge 1 -> edge 1 only. And we know with certainty that edge 1 will leave the source at 20 ns only. So, hold slack should not get bothered by the amount of jitter present at the clock source for single cycle timing paths.

Now, you understand the basics of  how jitter affects setup and hold slacks. We can state as below:

If the check being formed involves two different edges of same polarity (for instance, different rising edges), then, jitter in clock period will affect setup slack. Otherwise, it will not.

Now, can you guess the effect of jitter on setup and hold slacks for zero cycle timing paths?

Also, what will be the amount of pessimism needed to be taken into account for setup and hold slacks' calculations if the timing path is a multi-cycle path taking 2 cycles for setup and zero cycle for hold?

Also read:

• Interview questions related to clock jitter and duty cycle variations

Clock skew

Clock skew is one of the most important parameters of a good physical design implementation. Keeping the clock skew to a minimum is considered to be a good measure of clock tree synthesis. 

Definition of clock skew: Clock skew between two flip-flops represents the difference in arrival times of clock signal at the respective clock pins. If there is a timing path being formed between the two flip-flops, then we can attribute a sign to the clock skew. In that case, clock skew is given as:

Clock skew = (Arrival time at capture clock pin) - (Arrival time at launch clock pin)

Thus, based upon the sign of clock skew, we get two types of clock skew labelled as positive skew and negative skew.

Positive clock skew: If the clock arrival time at capture flip-flop is greater than that at launch flip-flop, clock skew is said to be positive. Assuming all buffers take the same delay, figure 1 shows a scenario of positive clock skew.

As shown in figure 1 above for the case of positive clock skew, flip-flop capturing data is getting delayed clock signal. So, the data that is launched gets additional time before it is captured at the next edge. So, setup check gets relaxed by the amount equivalent to clock skew. On the other hand, for hold check, the data has to be kept stable for an extra amount of time equal to the clock skew. So, hold check gets tightened in case clock skew is positive. The same is shown in figure 2 below.

Negative clock skew: Contrary to positive clock skew, if the clock arrival time at capture flip-flop is less than the launch flip-flop, clock skew is said to be negative. Figure 3 shows a scenario of negative clock skew as the launch flip-flop getting a delayed version of clock signal.



Since, the launching flip-flop is getting a delayed version of clock, the data launched gets less than one clock period to travel to the capturing flip-flop. So, negative clock skew makes setup check tighter by the magnitude of clock skew. On the other hand, for hold check, data has to be stable for less time after the arrival of clock edge. In other words, hold check gets relaxed by the same amount. Figure 4 below shows the scenario of negative clock skew.

Read next: Clock latency

Also read:

• All about clock signals
• Defining a clock signal in VHDL
• Virtual clock - purpose and timing

STA

Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circuit without actually simulating it. In this post, we have tried to list down all the posts that an STA engineer cannot do without. Please add your feedback in comments to make reading it a more meaningful experience.

• Setup and hold interview questions

• Clock gating concepts
• Setup time and hold time - static timing analysis - Definition and detailed discussion on setup time and hold time, setup hold violations and how to fix them

• Metastability - This post discusses the basics of metastability and how to avoid it.

• Problem: clock gating checks at a complex gate - An exercise to analyze the requirements of clock gating checks at a complex gate

• Lockup latch - The basics of lockup latch, both from timing and DFT perspective have been discussed in this post.

• Lockup latches vs. lockup registers - Provides an insight into the situations where lockup latches and lockup registers can be useful.

• Clock latency - Read this if you wish to get acquainted with the terminology related to clock latency

• Data checks - Non-sequential setup and hold checks have been discussed, very useful for beginners

• Modeling skew requirements with the help of data checks - Explains with an example how data checks can be used to maintain skew requirements

• What is static timing analysis - Defines static timing analysis and its scope

• Setup checks and hold checks for reg-to-reg paths - Discusses the default setup and hold checks for timing paths starting from and ending at registers

• Setup checks and hold checks for register-to-latch paths - Discusses the default setup and hold checks for timing paths starting from registers and ending at latches

• Setup checks and hold checks for latch-to-reg timing paths - Discussed the default setup and hold checks for timing paths starting from latches and ending at registers

• All about clock signals - Discusses the basics of clock signals

• Synchronizers - Different types of synchronizers have been discussed in detail

• Timing corners - dimensions in timing signoff - Highlights the importance of signing off in different corner-case scenarios

• Ensuring glitch-free propagation of clock - Discusses about the hazards that can occur, if there is a glitch in clock

• Clock switching and clock gating checks - The basics of clock gating check, and how to apply these is discussed

• Clock gating checks at a mux - How clock gating checks should be applied on a mux is discussed in detail

• False paths - what are they - This post discussed the basics of false paths and how to treat them

• Multicycle paths handling in STA - Basics of multicycle paths and how they are treated in STA

• All about multicycle paths in VLSI - Architecture specific description and handling of multicycle paths, a must read

• Propagation delay - Defines propagation delay and related terms

• Is it possible for a logic gate to have negative delay - Thought provoking post on whether a logic gate can have negative delay

• Worst slew propagation - Discusses the basics of worst slew propagation

• On-chip variations - Describes on-chip variations and the methods undertaken to deal with these

• Temperature inversion - Discusses the concept of temperature inversion and conductivity trends with temperature

• Can a net have negative delay - Describes how a net cannot have a negative delay

• Timing arcs - Discusses the basics of timing arcs, positive and negative unateness, cell arcs and net arcs etc.

• Time borrowing in latches - Discusses the basics of the concept of time borrowing

• Interesting problem - latches in series - Describes why it is essential to have alternate positive and negative latches for sequential operation

• Virtual clock - Explains the concept of virtual clock

• Minimum pulse width - Discusses about minimum pulse width checks

• Basics of latch timing - Definition of latch, setup time and hold timing of a latch, latch timing arcs are discussed