Clock gating checks in case of mux select transition when both clocks are running

PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. What are the architectural and STA considerations for the same?

SOLUTION:
This is a very good example to understand how clock gating checks work, although you may/may not find any practical application for the same. We have to toggle the select of the multiplexer such that there is no glitch at the output. Let us consider architectural considerations first:

Architectural considerations:

Launching flip-flop of 'select' signal: In the post clock gating checks at a multiplexer, we discussed that if there is a mux getting clock at its inputs and select as data, then, there are two possible scenarios:

• If the other clock is at state "0", then AND type check is formed and select has to launch from negative edge-triggered flip-flop

• If the other clock is at state "1", then OR type check is formed and select has to launch from positive edge-triggered flip-flop

Now, since both the clocks are running simultaneously, both with act as "other clock" for each other. Let us choose to keep both the clocks at state "0" when select toggles. The same discussion holds true for the other scenario as well, just that appropriate values will hold. Thus,

(i) Both clocks required to be at state '0' when clock toggles

(ii) There is AND-type clock gating check formed between 'select' and both clocks 

(iii) 'select' launches from negative edge-triggered flip-flop.

Valid negative edges when 'select' can toggle: Now, as mentioned above both the clocks should be zero when select toggles. Figure below shows the valid and invalid edges where 'select' can toggle. As it turns out, select can toggle only on edges labelled "VALID" as both "CLOCK" and "DIV_CLOCK" will be zero then.

 So, to ensure that "SEL" toggles only when DIV_CLOCK is "0", we can add logic to the input of the flip-flop launching "SEL" such that it allows to propagate "SEL" only when DIV_CLOCK is "0".

In the above diagram, flip-flop launching "SEL" will hold its value when DIV_CLOCK = 0. We have to keep in mind that this implementation is just a representation of what needs to be done. the actual implementation may be more complex than this depending upon the requirements.

Timing considerations: Now coming to the timing considerations, we need to ensure that the setup and hold conditions are met, which are as shown in the figure below:

Also read:

• Clock gating interview questions

Quiz : Clock gating check at a complex gate

Problem: Consider a complex gate with internal structure as shown in figure below. One of the inputs gets clock while all others get data signals. What all (and what type of) clock gating checks exist?

Figure:Problem figure

Solution: As we know, clock gating checks can be of AND type or OR type. We can find the type of clock gating check formed between a data and a clock signal by considering all other signals as constant. Since, all the 4 data signals control Clk in one or the other way, there are following clock gating checks formed:

      i)        Clock gating check between Data1 and Clk: As is evident, invert of Clk and Data1 meet at OR gate ‘6’. Hence, there is OR type check between invert of Clk and Data1. In other words, Data1 can change only when invert of Clk is high or Clk is low. Hence, there is AND type check formed at gate 6.

      ii)        Clock gating check between Data2 and Clk: Same as in case 1.

      iii)       Clock gating check between Data3 and Clk: There is AND type check between Data3 and Clk.

     iv)     Clock gating check between Data4 and CLK: As in 1 and 2, there is AND type check between Data4 and Clk.

Also read: 

• Clock gating interview questions

Clock gating checks

Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. And a number of control signals are there which control these clocks. These signals are behind switching on and off the design. Let us say, we have a simple design as shown in the figure below. Pin ‘SEL’ selects between two clocks. Also, ‘EN’ selects if clock will be propagating to the sub-design or not. Similarly, there are signals that decide what, when, where and how for propagation of clocks. Some of these controlling signals may be static while some of these might be dynamic. Even with all this, these signals should not play with waveform of the clock; i.e. these should not cause any glitch in clock path. There are both architectural as well as timing care-abouts that are to be taken care of while designing for signals toggling in clock paths. This scenario is widely known as ‘clock gating’. The timing checks that need to be modeled in timing constraints are known as ‘clock gating checks’.

Figure 1: A simplest clocking structure

Definition of clock gating check: A clock gating check is a constraint, either applied or inferred automatically by tool, that ensures that the clock will propagate without any glitch through the gate.

Types of clock gating checks: Fundamentally, all clock gating checks can be categorized into two types:

AND type clock gating check: Let us say we have a 2-input AND gate in which one of the inputs has a clock and the other input has a data which will toggle while the clock is still on.

Figure 2: AND type clock gating check; EN signal
controlling CLK_IN through AND gate

Since, the clock is free-running, we have to ensure that the change of state of enable signal does not cause the output of the AND gate to toggle. This is only possible if the enable input toggles when clock is at ‘0’ state. As is shown in figure 3 below, if ‘EN’ toggles when ‘CLK_IN’ is high, the clock pulse gets clipped. In other words, we do not get full duty cycle of the clock. Thus, this is a functional architectural miss causing glitch in clock path. As is evident in figure 4, if ‘EN’ changes during ‘CLK_IN’ are low, there is no change in clock duty cycle. Hence, this is the right way to gate a clock signal with an enable signal; i.e. make the enable toggle only when clock is low.

Figure 3: Clock being clipped when ‘EN’ changes when ‘CLK_IN’ is high

Figure 4: Clock waveform not being altered when ‘EN’ changes when ‘CLK_IN’ is low

Theoretically, ‘EN’ can launch from either positive edge-triggered or negative edge-triggered flops. In case ‘EN’ is launched by a positive edge-triggered flop, the setup and hold checks will be as shown in figure 5. As shown, setup check in this case is on the next positive edge and hold check is on next negative edge. However, the ratio of maximum and minimum delays of cells in extreme operating conditions may be as high as 3. So, architecturally, this situation is not possible to guarantee the clock to pass under all conditions.

Figure 5: Clock gating setup and hold checks on AND gate when 'EN' launches from a positive edge-triggered flip-flop

On the contrary, if ‘EN’ launches from a negative edge-triggered flip-flop, setup check are formed with respect to the next rising edge and hold check is on the same falling edge (zero-cycle) as that of the launch edge. The same is shown in figure 6. Since, in this case, hold check is 0 cycle, both the checks are possible to be met for all operating conditions; hence, this solution will guarantee the clock to pass under all operating condition provided the setup check is met for worst case condition. The inactive clock state, as evident, in this case, is '0'.

Figure 6: Clock gating setup and hold checks on AND gate when ‘EN’ launches from negative edge-triggered flip-flop

Figure 7: An OR gate controlling a clock signal 'CLK_IN'

OR type clock gating check: Similarly, since the off-state of OR gate is 1, the enable for an OR type clock gating check can change only when the clock is at ‘1’ state. That is, we have to ensure that the change of state of enable signal does not cause the output of the OR gate to toggle. Figure 9 below shows if ‘EN’ toggles when ‘CLK_IN’ is high, there is no change in duty cycle. However, if ‘EN’ toggles when ‘CLK_IN’ is low (figure 8), the clock pulse gets clipped. Thus, ‘EN’ must be allowed to toggle only when ‘CLK_IN’ is high.

Figure 8: Clock being clipped when 'EN' changes when 'CLK_IN' is low

Figure 9: Clock waveform not being altered when 'EN' changes when 'CLK_IN' is low

As in case of AND gate, here also, ‘EN’ can launch from either positive or negative edge flops. In case ‘EN’ launches from negative edge-triggered flop, the setup and hold checks will be as shown in the figure 10. The setup check is on the next negative edge and hold check is on the next positive edge. As discussed earlier, it cannot guarantee the glitch less propagation of clock.

Figure 10: Clock gating setup and hold checks on OR gate when ‘EN’ launches from negative edge-triggered flip-flop

If ‘EN’ launches from a positive edge-triggered flip-flop, setup check is with respect to next falling edge and hold check is on the same rising edge as that of the launch edge. The same is shown in figure 11. Since, the hold check is 0 cycle, both setup and hold checks are guaranteed to be met under all operating conditions provided the path has been optimized to meet setup check for worst case condition. The inactive clock state, evidently, in this case, is '1'.

Figure 11: Clock gating setup and hold checks on OR gate when 'EN' launches from a positive edge-triggered flip-flop

We have, thus far, discussed two fundamental types of clock gating checks. There may be complex combinational cells other than 2-input AND or OR gates. However, for these cells, too, the checks we have to meet between the clock and enable pins will be of the above two types only. If the enable can change during low phase of the clock only, it is said to be AND type clock gating check and vice-versa.

SDC command for application of clock gating checks: In STA, clock gating checks can be applied with the help of SDC command set_clock_gating_check.

Also read:

• Clock gating interview questions