VLSI UNIVERSE

Showing posts with label Static Timing Analysis Interview Questions. Show all posts
Showing posts with label Static Timing Analysis Interview Questions. Show all posts

Clock gating checks in case of mux select transition when both clocks are running

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PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. W...
16 comments:

What is the difference between a normal buffer and clock buffer?

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A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a re...
19 comments:

Can jitter in clock effect setup and hold violations?

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First of all, we need to understand what is meant by jitter. In most simplistic language, jitter is the uncertainty of a clock source in p...
8 comments:

Clock skew

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Clock skew is one of the most important parameters of a good physical design implementation. Keeping the clock skew to a minimum is consi...
2 comments:

STA

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Static timing analysis (STA) is a vast domain involving many sub-fields. It involves computing the limits of delay of elements in the circ...
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