Can we use discrete latches and AND/OR gates instead of ICG?

In the post, Integated Clock Gating Cell, we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to relax hold timing for clock gating check. And we discussed that it gives benefits for area, power and timing. Let us discuss how area, power and timing are saved. We will discuss only for the case of AND gate, the same will follow for OR gate.

1. Architectural benefits - simplicity in clock handling: By introducing ICGs in place of discrete gates, you dont have to worry about the launch edge of the signal while writing RTL (for details, see here). One can always launch the signal from positive edge-triggered flip-flop for timing and architectural simplicity without worrying about possibility of glitch in clock path due to wrong polarity flip-flop launching enable signal.

2. Benefits in area and power: Having custom module allows for better utilization of resources inside the custom ICG module; hence, it is expected to have lesser power than a latch and an AND gate combined.

3. Benefits in timing: Having the path from latch -> AND inside ICG saves us from having to meet these paths individually, which could take a lot of effort with discrete latch and AND gate. Also, it allows for latch to have almost full time borrow, thereby making almost a full cycle path from a positive edge-triggered flip-flop to ICG.

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• Clock gating interview questions

Clock gating checks in case of mux select transition when both clocks are running

PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. What are the architectural and STA considerations for the same?

SOLUTION:
This is a very good example to understand how clock gating checks work, although you may/may not find any practical application for the same. We have to toggle the select of the multiplexer such that there is no glitch at the output. Let us consider architectural considerations first:

Architectural considerations:

Launching flip-flop of 'select' signal: In the post clock gating checks at a multiplexer, we discussed that if there is a mux getting clock at its inputs and select as data, then, there are two possible scenarios:

• If the other clock is at state "0", then AND type check is formed and select has to launch from negative edge-triggered flip-flop

• If the other clock is at state "1", then OR type check is formed and select has to launch from positive edge-triggered flip-flop

Now, since both the clocks are running simultaneously, both with act as "other clock" for each other. Let us choose to keep both the clocks at state "0" when select toggles. The same discussion holds true for the other scenario as well, just that appropriate values will hold. Thus,

(i) Both clocks required to be at state '0' when clock toggles

(ii) There is AND-type clock gating check formed between 'select' and both clocks 

(iii) 'select' launches from negative edge-triggered flip-flop.

Valid negative edges when 'select' can toggle: Now, as mentioned above both the clocks should be zero when select toggles. Figure below shows the valid and invalid edges where 'select' can toggle. As it turns out, select can toggle only on edges labelled "VALID" as both "CLOCK" and "DIV_CLOCK" will be zero then.

 So, to ensure that "SEL" toggles only when DIV_CLOCK is "0", we can add logic to the input of the flip-flop launching "SEL" such that it allows to propagate "SEL" only when DIV_CLOCK is "0".

In the above diagram, flip-flop launching "SEL" will hold its value when DIV_CLOCK = 0. We have to keep in mind that this implementation is just a representation of what needs to be done. the actual implementation may be more complex than this depending upon the requirements.

Timing considerations: Now coming to the timing considerations, we need to ensure that the setup and hold conditions are met, which are as shown in the figure below:

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• Clock gating interview questions

Design problem: Clock gating for a shift register

Problem: There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportunity to clock gate the module.

 Mode selection bits ("S1" and "S0") are controlling the operation of this shift register with following settings:

Solution: From the basics of clock gating, we know that if the stae of a flip-flop is not chaging, there lies an opportunity to gate its clock. Observing the table, we see that state of all flip-flops does not change when "S1,S0" are either "00" or "11". So, when mode selection bits are corresponding to these values, we can gate the clock to this shift register. Or, we can say that clock to the module should reach only when (S1 xor S0) is equal to 1.

Can you relate the timing of S1 and S0? Should they be coming from positive edge-triggered flip-flop or negative edge-triggered flip-flop? Clock gating checks explains the timing of clock gating signals with respect to clock.

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• Clock gating interview questions

Quiz : Clock gating check at a complex gate

Problem: Consider a complex gate with internal structure as shown in figure below. One of the inputs gets clock while all others get data signals. What all (and what type of) clock gating checks exist?

Figure:Problem figure

Solution: As we know, clock gating checks can be of AND type or OR type. We can find the type of clock gating check formed between a data and a clock signal by considering all other signals as constant. Since, all the 4 data signals control Clk in one or the other way, there are following clock gating checks formed:

      i)        Clock gating check between Data1 and Clk: As is evident, invert of Clk and Data1 meet at OR gate ‘6’. Hence, there is OR type check between invert of Clk and Data1. In other words, Data1 can change only when invert of Clk is high or Clk is low. Hence, there is AND type check formed at gate 6.

      ii)        Clock gating check between Data2 and Clk: Same as in case 1.

      iii)       Clock gating check between Data3 and Clk: There is AND type check between Data3 and Clk.

     iv)     Clock gating check between Data4 and CLK: As in 1 and 2, there is AND type check between Data4 and Clk.

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• Clock gating interview questions

Clock gating checks at a multiplexer (MUX)

In the post 'clock switching and clock gating checks', we discussed why clock gating checks are needed. Also, we discussed the two basic types of clock gating checks. Let us go one step further. The most common types of combinational cells with dynamic clock switching encountered in today’s designs are multiplexers. We will be discussing the clock gating checks at a multiplexer. For simplicity, let us say, we have a 2-input multiplexer with 1 select pin. There can be two cases:

Case 1: Data signal at the select pin of MUX used to select between two clocks

Figure 1: MUX with Data as select dynamically selecting the clock signal to propagate to output

This scenario is shown in figure 1 above. This situation normally arises when ‘Data’ acts as clock select and dynamically selects which of the two clocks will propagate to the output. The function of the MUX is given as:

CLK_OUT = Data.CLK1 + Data’.CLK2

The internal structure (in terms of basic gates) is as shown below in figure 2.

Figure 2: Internal structure of mux in figure 1

There will be two clock gating checks formed:

1. Between CLK1 and Data: There are two cases to be considered for this scenario:

• When CLK2 is at state '0': In this scenario, if the data toggles when CLK1 is '0', it will pass without any glitches. On the other hand, there will be a glitch if data toggles when CLK1 is '1'. Thus, the mux acts as AND gate and there will be AND-type clock gating check.
• When CLK2 is '1': In this scenario, if data toggles when CLK1 is '1', it will pass without any glitches; and will produce a glitch if toggled when CLK1 is '0'. In other words, MUX acts as an OR gate; hence, OR-type clock gating check will be formed in this case.

1. 2. Between CLK2 and Data: This scenario also follows scenario '1'. And the type of clock gating check formed will be determined by the state of inactive clock.
2. 1. 1. 
         
   2. Thus, the type of clock gating check to be applied, in this case, depends upon the inactive state of the other clock. If it is '0', AND-type check will be formed. On the other hand, if it is '1', OR-type check will be formed.

Case 2: Clock signal is at select line. This situation is most common in case of Mux-based configurable clock dividers wherein output clock waveform is a function of the two data values.

Figure 3: Combination of Data1 and Data2 determines if CLK or CLK' will propagate to the output

In this case too, there will be two kinds of clock gating checks formed:

i)                  Between CLK and Data1: Here, both CLK and Data1 are input to a 2-input AND gate, hence, there will be AND type check between CLK and Data1. The following SDC command will serve the purpose:

set_clock_gating_check -high 0.1 [get_pins MUX/Data1]

The above command will constrain an AND-type clock gating check of 100 ps on Data1 pin.

ii)                    Between CLK and Data2: As is evident from figure 3, there will be AND type check between CLK’ and Data2. This means Data2 can change only when CLK’ is low. In other words, Data2 can change only when CLK is high. This means there is OR type check between CLK and Data2. The following command will do the job:

set_clock_gating_check -low 0.1 [get_pins MUX/Data2]

The above command will constrain an  OR-type clock gating check of 100 ps on Data2 pin.

Thus, we have discussed how there are clock gating checks formed between different signals of a MUX. 

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• Clock gating interview questions

Clock gating checks

Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. And a number of control signals are there which control these clocks. These signals are behind switching on and off the design. Let us say, we have a simple design as shown in the figure below. Pin ‘SEL’ selects between two clocks. Also, ‘EN’ selects if clock will be propagating to the sub-design or not. Similarly, there are signals that decide what, when, where and how for propagation of clocks. Some of these controlling signals may be static while some of these might be dynamic. Even with all this, these signals should not play with waveform of the clock; i.e. these should not cause any glitch in clock path. There are both architectural as well as timing care-abouts that are to be taken care of while designing for signals toggling in clock paths. This scenario is widely known as ‘clock gating’. The timing checks that need to be modeled in timing constraints are known as ‘clock gating checks’.

Figure 1: A simplest clocking structure

Definition of clock gating check: A clock gating check is a constraint, either applied or inferred automatically by tool, that ensures that the clock will propagate without any glitch through the gate.

Types of clock gating checks: Fundamentally, all clock gating checks can be categorized into two types:

AND type clock gating check: Let us say we have a 2-input AND gate in which one of the inputs has a clock and the other input has a data which will toggle while the clock is still on.

Figure 2: AND type clock gating check; EN signal
controlling CLK_IN through AND gate

Since, the clock is free-running, we have to ensure that the change of state of enable signal does not cause the output of the AND gate to toggle. This is only possible if the enable input toggles when clock is at ‘0’ state. As is shown in figure 3 below, if ‘EN’ toggles when ‘CLK_IN’ is high, the clock pulse gets clipped. In other words, we do not get full duty cycle of the clock. Thus, this is a functional architectural miss causing glitch in clock path. As is evident in figure 4, if ‘EN’ changes during ‘CLK_IN’ are low, there is no change in clock duty cycle. Hence, this is the right way to gate a clock signal with an enable signal; i.e. make the enable toggle only when clock is low.

Figure 3: Clock being clipped when ‘EN’ changes when ‘CLK_IN’ is high

Figure 4: Clock waveform not being altered when ‘EN’ changes when ‘CLK_IN’ is low

Theoretically, ‘EN’ can launch from either positive edge-triggered or negative edge-triggered flops. In case ‘EN’ is launched by a positive edge-triggered flop, the setup and hold checks will be as shown in figure 5. As shown, setup check in this case is on the next positive edge and hold check is on next negative edge. However, the ratio of maximum and minimum delays of cells in extreme operating conditions may be as high as 3. So, architecturally, this situation is not possible to guarantee the clock to pass under all conditions.

Figure 5: Clock gating setup and hold checks on AND gate when 'EN' launches from a positive edge-triggered flip-flop

On the contrary, if ‘EN’ launches from a negative edge-triggered flip-flop, setup check are formed with respect to the next rising edge and hold check is on the same falling edge (zero-cycle) as that of the launch edge. The same is shown in figure 6. Since, in this case, hold check is 0 cycle, both the checks are possible to be met for all operating conditions; hence, this solution will guarantee the clock to pass under all operating condition provided the setup check is met for worst case condition. The inactive clock state, as evident, in this case, is '0'.

Figure 6: Clock gating setup and hold checks on AND gate when ‘EN’ launches from negative edge-triggered flip-flop

Figure 7: An OR gate controlling a clock signal 'CLK_IN'

OR type clock gating check: Similarly, since the off-state of OR gate is 1, the enable for an OR type clock gating check can change only when the clock is at ‘1’ state. That is, we have to ensure that the change of state of enable signal does not cause the output of the OR gate to toggle. Figure 9 below shows if ‘EN’ toggles when ‘CLK_IN’ is high, there is no change in duty cycle. However, if ‘EN’ toggles when ‘CLK_IN’ is low (figure 8), the clock pulse gets clipped. Thus, ‘EN’ must be allowed to toggle only when ‘CLK_IN’ is high.

Figure 8: Clock being clipped when 'EN' changes when 'CLK_IN' is low

Figure 9: Clock waveform not being altered when 'EN' changes when 'CLK_IN' is low

As in case of AND gate, here also, ‘EN’ can launch from either positive or negative edge flops. In case ‘EN’ launches from negative edge-triggered flop, the setup and hold checks will be as shown in the figure 10. The setup check is on the next negative edge and hold check is on the next positive edge. As discussed earlier, it cannot guarantee the glitch less propagation of clock.

Figure 10: Clock gating setup and hold checks on OR gate when ‘EN’ launches from negative edge-triggered flip-flop

If ‘EN’ launches from a positive edge-triggered flip-flop, setup check is with respect to next falling edge and hold check is on the same rising edge as that of the launch edge. The same is shown in figure 11. Since, the hold check is 0 cycle, both setup and hold checks are guaranteed to be met under all operating conditions provided the path has been optimized to meet setup check for worst case condition. The inactive clock state, evidently, in this case, is '1'.

Figure 11: Clock gating setup and hold checks on OR gate when 'EN' launches from a positive edge-triggered flip-flop

We have, thus far, discussed two fundamental types of clock gating checks. There may be complex combinational cells other than 2-input AND or OR gates. However, for these cells, too, the checks we have to meet between the clock and enable pins will be of the above two types only. If the enable can change during low phase of the clock only, it is said to be AND type clock gating check and vice-versa.

SDC command for application of clock gating checks: In STA, clock gating checks can be applied with the help of SDC command set_clock_gating_check.

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• Clock gating interview questions

Need for clock gating checks - need for glitchless clock propagation

One of the most important things in designs is to ensure glitch free propagation of clocks. Even a single glitch in clock path can cause the chip to be metastable and even fail. A glitch is any unwanted clock pulse that may cause the sequential cells to consider it as an actual clock pulse. Thus, a glitch can put your device in an unwanted state that is functionally never possible. That is why; there should never be a glitch in clock path. Every effort should be done by designers to minimize its probability. The figure below shows a flip-flop receiving a data signal and a clock signal; if there is some glitch (unwanted change of state) in clock, it will take it as a real clock edge and latch the data to its output. However, if the pulse is too small, the data may not propagate properly to output and the flop may go metastable.

Figure showing functional glitch in clock path

There may be following kind of cells present in clock path:

     1)      Buffers/inverters: Since, there is only one input for a buffer/inverter, the glitch may occur on the output of these gates only through coupling with other signals in the vicinity. If we ensure that the buffer/inverter has good drive strength and that the load and transition at its output are under a certain limit, we can be certain that the glitch will not occur.

      2)   Combinational gates: There can be combinational gates other than buffers/inverters in clock path, say, a 2-input AND gate having an enable signal that tells if the clock is to be propagated or not. Each combinational gate might have one or more clocks and data/enable pins. Let us say, we have a two input AND gate with one input as clock and the other acting as an enable to the clock. We can have following cases possible:

i)             The other input is static: By static, we mean the other input will not change on the fly. In other words, whenever the enable will change, the clock will be off. So, enable will not cause the waveform at the output of the gate to change. This case is similar to a buffer/inverter as the other input will not cause the shape of the output pulse to change.

ii)                The other input is toggling: In this case, the enable might affect the waveform at the output of the gate to change. To ensure that there is not glitch causes by this, there are certain requirements related to skew between data and clock to be met, which will be discussed later in the text. These requirements are termed as clock gating checks.

3   3)    Sequential gates: There may also be sequential gates in clock path, say, a flop, a latch or an integrated clock gating cell with the clock at its clock input and the enable for the clock will be coming at its data input. The output of these cells will be a clock pulse. For these also, two cases are possible as in case 2. In other words, if the enable changes when clock is off, the enable is said to be static. In that case, the output either has clock or does not have clock. On the other hand, if the input is toggling while clock is there at the input, we may get away by meeting the setup and hold checks for the enable signal with respect to clock input.

As discussed above, to ensure a glitch free propagation of clock at the output of the combinational gates, we have to ensure some timing requirements between the enable signal and clock. These timing requirements ensure that there is no functionally unwanted pulse in clock path. If we ensure these timing requirements are met, there will be no functional glitch in clock path. However, glitches due to crosstalk between signals can still occur. There are other techniques to prevent glitches due to crosstalk. The functional glitches in clock path can be prevented by ensuring the above discussed timing requirements. In STA, these requirements are enforced on designs through timing checks known as clock gating checks. By ensuring these checks are applied and taken care of properly, an STA engineer can sign-off for functional glitches. In later posts, we will be dealing with these checks in more details.

Also read:

• All about clock signals
• Clock gating checks
• Clock gating checks at a MUX
• Setup time and hold time - static timing analysis
• Worst slew propagation