Clock gating checks at a multiplexer (MUX)

In the post 'clock switching and clock gating checks', we discussed why clock gating checks are needed. Also, we discussed the two basic types of clock gating checks. Let us go one step further. The most common types of combinational cells with dynamic clock switching encountered in today’s designs are multiplexers. We will be discussing the clock gating checks at a multiplexer. For simplicity, let us say, we have a 2-input multiplexer with 1 select pin. There can be two cases:

Case 1: Data signal at the select pin of MUX used to select between two clocks

Figure 1: MUX with Data as select dynamically selecting the clock signal to propagate to output

This scenario is shown in figure 1 above. This situation normally arises when ‘Data’ acts as clock select and dynamically selects which of the two clocks will propagate to the output. The function of the MUX is given as:

CLK_OUT = Data.CLK1 + Data’.CLK2

The internal structure (in terms of basic gates) is as shown below in figure 2.

Figure 2: Internal structure of mux in figure 1

There will be two clock gating checks formed:

1. Between CLK1 and Data: There are two cases to be considered for this scenario:

• When CLK2 is at state '0': In this scenario, if the data toggles when CLK1 is '0', it will pass without any glitches. On the other hand, there will be a glitch if data toggles when CLK1 is '1'. Thus, the mux acts as AND gate and there will be AND-type clock gating check.
• When CLK2 is '1': In this scenario, if data toggles when CLK1 is '1', it will pass without any glitches; and will produce a glitch if toggled when CLK1 is '0'. In other words, MUX acts as an OR gate; hence, OR-type clock gating check will be formed in this case.

1. 2. Between CLK2 and Data: This scenario also follows scenario '1'. And the type of clock gating check formed will be determined by the state of inactive clock.
2. 1. 1. 
         
   2. Thus, the type of clock gating check to be applied, in this case, depends upon the inactive state of the other clock. If it is '0', AND-type check will be formed. On the other hand, if it is '1', OR-type check will be formed.

Case 2: Clock signal is at select line. This situation is most common in case of Mux-based configurable clock dividers wherein output clock waveform is a function of the two data values.

Figure 3: Combination of Data1 and Data2 determines if CLK or CLK' will propagate to the output

In this case too, there will be two kinds of clock gating checks formed:

i)                  Between CLK and Data1: Here, both CLK and Data1 are input to a 2-input AND gate, hence, there will be AND type check between CLK and Data1. The following SDC command will serve the purpose:

set_clock_gating_check -high 0.1 [get_pins MUX/Data1]

The above command will constrain an AND-type clock gating check of 100 ps on Data1 pin.

ii)                    Between CLK and Data2: As is evident from figure 3, there will be AND type check between CLK’ and Data2. This means Data2 can change only when CLK’ is low. In other words, Data2 can change only when CLK is high. This means there is OR type check between CLK and Data2. The following command will do the job:

set_clock_gating_check -low 0.1 [get_pins MUX/Data2]

The above command will constrain an  OR-type clock gating check of 100 ps on Data2 pin.

Thus, we have discussed how there are clock gating checks formed between different signals of a MUX. 

Also read: 

• Clock gating interview questions

Need for clock gating checks - need for glitchless clock propagation

One of the most important things in designs is to ensure glitch free propagation of clocks. Even a single glitch in clock path can cause the chip to be metastable and even fail. A glitch is any unwanted clock pulse that may cause the sequential cells to consider it as an actual clock pulse. Thus, a glitch can put your device in an unwanted state that is functionally never possible. That is why; there should never be a glitch in clock path. Every effort should be done by designers to minimize its probability. The figure below shows a flip-flop receiving a data signal and a clock signal; if there is some glitch (unwanted change of state) in clock, it will take it as a real clock edge and latch the data to its output. However, if the pulse is too small, the data may not propagate properly to output and the flop may go metastable.

Figure showing functional glitch in clock path

There may be following kind of cells present in clock path:

     1)      Buffers/inverters: Since, there is only one input for a buffer/inverter, the glitch may occur on the output of these gates only through coupling with other signals in the vicinity. If we ensure that the buffer/inverter has good drive strength and that the load and transition at its output are under a certain limit, we can be certain that the glitch will not occur.

      2)   Combinational gates: There can be combinational gates other than buffers/inverters in clock path, say, a 2-input AND gate having an enable signal that tells if the clock is to be propagated or not. Each combinational gate might have one or more clocks and data/enable pins. Let us say, we have a two input AND gate with one input as clock and the other acting as an enable to the clock. We can have following cases possible:

i)             The other input is static: By static, we mean the other input will not change on the fly. In other words, whenever the enable will change, the clock will be off. So, enable will not cause the waveform at the output of the gate to change. This case is similar to a buffer/inverter as the other input will not cause the shape of the output pulse to change.

ii)                The other input is toggling: In this case, the enable might affect the waveform at the output of the gate to change. To ensure that there is not glitch causes by this, there are certain requirements related to skew between data and clock to be met, which will be discussed later in the text. These requirements are termed as clock gating checks.

3   3)    Sequential gates: There may also be sequential gates in clock path, say, a flop, a latch or an integrated clock gating cell with the clock at its clock input and the enable for the clock will be coming at its data input. The output of these cells will be a clock pulse. For these also, two cases are possible as in case 2. In other words, if the enable changes when clock is off, the enable is said to be static. In that case, the output either has clock or does not have clock. On the other hand, if the input is toggling while clock is there at the input, we may get away by meeting the setup and hold checks for the enable signal with respect to clock input.

As discussed above, to ensure a glitch free propagation of clock at the output of the combinational gates, we have to ensure some timing requirements between the enable signal and clock. These timing requirements ensure that there is no functionally unwanted pulse in clock path. If we ensure these timing requirements are met, there will be no functional glitch in clock path. However, glitches due to crosstalk between signals can still occur. There are other techniques to prevent glitches due to crosstalk. The functional glitches in clock path can be prevented by ensuring the above discussed timing requirements. In STA, these requirements are enforced on designs through timing checks known as clock gating checks. By ensuring these checks are applied and taken care of properly, an STA engineer can sign-off for functional glitches. In later posts, we will be dealing with these checks in more details.

Also read:

• All about clock signals
• Clock gating checks
• Clock gating checks at a MUX
• Setup time and hold time - static timing analysis
• Worst slew propagation