Showing posts with label Clock gating interview questions. Show all posts
Showing posts with label Clock gating interview questions. Show all posts

Can we use discrete latches and AND/OR gates instead of ICG?

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In the post, Integated Clock Gating Cell , we discussed that an ICG has a negative level-sensitive latch preceding an AND gate in order to...

Clock gating checks in case of mux select transition when both clocks are running

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PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. W...
16 comments:

Design problem: Clock gating for a shift register

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Problem : There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportun...

Quiz : Clock gating check at a complex gate

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Problem: Consider a complex gate with internal structure as shown in figure below. One of the inputs gets clock while all others get data ...

Clock gating checks at a multiplexer (MUX)

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In the post ' clock switching and clock gating checks ', we discussed why clock gating checks are needed. Also, we discussed the t...
8 comments:

Clock gating checks

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Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. ...
15 comments:

Need for clock gating checks - need for glitchless clock propagation

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One of the most important things in designs is to ensure glitch free propagation of clocks. Even a single glitch in clock path can cause...