In general, race condition refers
to a situation in which the result depends upon the sequence in which events
happen. In particular, a race condition occurs when a system/device is designed
assuming a particular sequence of events without taking steps to ensure it. In
logic gates, it happens when the inputs arrive at the gate in a sequence not
assumed while deriving the function. This results, sometimes, in the anomalous
behavior of the logic gate because of the unexpected dependence on the sequence
of arrival of inputs. Since, the function of the logic gate is calculated
assuming static inputs; the order of arrival may have impact on the output. We
can consider race condition as a situation in which two or more signals are
racing to have their effect on the output. This is how; race condition derives
its name.
For a very simple example,
consider the following logic function-
Z = A . A’
 | |||||
| Figure 1: An example digital circuit having race condition |
Theoretically, the output will
always be ‘0’. However, this is true only if the non-inverted portion of the
signal has greater delay in reaching the AND gate (we have considered ‘0’ ->
‘1’ transition of the input signal ‘A’). As shown in the figure above, the
signal passing through inverter will have some delay of its own. If the signal
through inverter reaches the AND gate later than the one without inverter,
there will be a glitch as shown in the figure 2. For ‘1’ -> ‘0’ transition,
the opposite will happen.
 |
| Figure 2: Glitch caused at the output of AND gate due to inverted signal being delayed than non-inverted signal |
What
can be the consequences: If the condition for race is violated, the design
may enter an undefined state, the one which might not have been considered
while designing. Hence, the whole system will malfunction in such a scenario
leading to failure. It might be the case that some elements in the design enter
metastable state, which can further cause problems. Hence, it is very important
to give proper consideration to race conditions.
How
can we prevent race condition: Normally, in digital designs, as long
as setup and hold checks are met for each flip-flop, we do not need to worry
about the race conditions in the design under consideration. But, there are
some conditions like the output of the above AND gate might be used as a clock
for some flop. In that case, we need to consider the race condition. We need to
have proper sequencing of signals so as to have the desired output. Had the
above case been in reality, it might be wise to delay the non-inverted signal. Race
conditions in the design can be eliminated by using proper design techniques (e.g.
K-map). Using these, designers and recognize and eliminate the race conditions
before they cause problems.
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