Static
timing analysis of a design is performed to estimate its working frequency
after the design has been fabricated. Nominal delays of the logic gates as per
characterization are calculated and some pessimism is applied above that to see
if there will be any setup and/or hold violation at the target frequency.
However, all the transistors manufactured are not alike. Also, not all the
transistors receive the same voltage and are at same temperature. The characterized delay is just the delay of
which there is maximum probability. The delay variation of a typical sample of
transistors on silicon follows the curve as shown in figure 1. As is shown,
most of the transistors have nominal characteristics. Typically, timing signoff
is carried out with some margin. By doing this, the designer is trying to
ensure that more number of transistors are covered. There is direct
relationship between the margin and yield. Greater the margin taken, larger is
the yield. However, after a certain point, there is not much increase in yield
by increasing margins. In that case, it adds more cost to the designer than it
saves by increase in yield. Therefore, margins should be applied so as to give
maximum profits.
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| Number of transistors v/s delay for a typical silicon transistors sample |
We
have discussed above how variations in characteristics of transistors are taken
care of in STA. These variations in transistors’ characteristics as
fabricated on silicon are known as OCV (On-Chip Variations). The reason for
OCV, as discussed above also, is that all transistors on-chip are not alike in
geometry, in their surroundings, and position with respect to power supply. The
variations are mainly caused by three factors:
- Process
variations: The process of fabrication includes diffusion, drawing out of
metal wires, gate drawing etc. The diffusion density is not uniform throughout
wafer. Also, the width of metal wire is not constant. Let us say, the width is
1um +- 20 nm. So, the metal delays are bound to be within a range rather than a
single value. Similarly, diffusion regions for all transistors will not have
exactly same diffusion concentrations. So, all transistors are expected to have
somewhat different characteristics.
- Voltage
variation: Power is distributed to all transistors on the chip with the help
of a power grid. The power grid has its own resistance and capacitance. So,
there is voltage drop along the power grid. Those transistors situated close to
power source (or those having lesser resistive paths from power source) receive
larger voltage as compared to other transistors. That is why, there is variation
seen across transistors for delay.
- Temperature
variation: Similarly, all the transistors on the same chip cannot have same
temperature. So, there are variations in characteristics due to variation in
temperatures across the chip.
How to take care of OCV: To
tackle OCV, the STA for the design is closed with some margins. There are
various margining methodologies available. One of these is applying a flat
margin over whole design. However, this is over pessimistic since some cells
may be more prone to variations than others. Another approach is applying cell
based margins based on silicon data as what cells are more prone to variations.
There also exist methodologies based on different theories e.g. location based
margins and statistically calculated margins. As advances are happening in STA,
more accurate and faster discoveries are coming into existence.