As we discussed
in ‘’Is
it possible for a logic gate to have negative propagation delay”, a logic
cell can have negative propagation delay. However, the only condition we
mentioned was that the transition at the output pin should be improved drastically
so that 50% level at output is reached before 50% level of input waveform.
In other words,
the only condition for negative delay is to have improvement in slew. As we
know, a net has only passive parasitic in the form of parasitic resistances and
capacitances. Passive elements can only degrade the transition as they cannot
provide energy (assuming no crosstalk); rather can only dissipate it. In other words, it is not
possible for a net to have negative propagation delay.
However, we can have negative delay for a net, if there is crosstalk, as crosstalk can improve the transition on a net. In other words, in the presence of crosstalk, we can have 50% level at output reached before 50% level at input; hence, negative propagation delay of a net.
Also read:
- Bubble errors and bubble error correction
- Noise margins
- Can hold be frequency dependant
- Worst slew propagation
- Latchup in CMOS devices