Why NAND structures are preferred over NOR ones?

Both NAND and NOR are classified as universal gates, but we see that NAND is preferred over NOR in CMOS logic structures. Let us discuss why it is so:

We know that when output is at logic 1, pull up structure for the output stage is on and it provides a path from VDD to output. Similarly, pull down structure provides a path from GND to output when output is logic 0. Pull up and pull down resistances are one of major factor in determining the speed of cell. The inverse of pull up and pull down resistances are called output high drive and output low drive of the cell respectively. In general, cells are designed to have similar drive strength of pull up and pull down structures to have comparable rise and fall time.

NMOS has half the resistance of an equal sized PMOS. let us say resistance of a given sized NMOS is R then resistance of  PMOS of same size will be 2R. In NAND gate, two NMOS are connected in series and two PMOS are connected in parallel. So, pull up and pull down resistances will be:

            Pull up resistance = 2R || 2R = R
            Pull down resistance = R + R = 2R

On the other hand, in a NOR gate, two NMOS are connected in parallel and two PMOS are connected in series. The pull-up and pull-down resistances, now, will be:

            Pull up resistance = 2R + 2R = 4R
            Pull down resistance = R || R = R/2

NAND gate has better ratio of output high drive and output low drive as compared to NOR gate. Hence NAND gate is preferred over NOR.

To use NOR gate as universal gate either pull up or pull down structure has to be resized(decrease the length of PMOS cells or increase length of NMOS cells) to have similar resistance as resistance is directly proportional to length (length of channel here).

Also read:

• XOR gate using NAND
• What is static timing analysis
• Propagation delay in logic gates

Divide by 2 clock in VHDL

Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequency as compared to input clock. A flip-flop with its inverted output fed back to its input serves as a divide-by-2 circuit. Figure 1 shows the schematic representation for the same.

Divide by 2 clock circuit

                                          

Following is the code for a divide-by-2 circuit.

-- This module is for a basic divide by 2 in VHDL.

library ieee;

use ieee.std_logic_1164.all;

entity div2 is

                port (

                                reset : in std_logic;

                                clk_in : in std_logic;

                                clk_out : out std_logic

                );

end div2;

-- Architecture definition for divide by 2 circuit

architecture behavior of div2 is
signal clk_state : std_logic;

begin

                process (clk_in,reset)

                begin

                                if reset = '1' then

                                                clk_state <= '0';

                                elsif clk_in'event and clk_in = '1' then

                                                clk_state <= not clk_state;

                                end if;

                end process;
clk_out <= clk_state;

end architecture;

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