As we know, depletion
MOSFET conducts current even with gate and source at same voltage level. To
cut-off the current in depletion MOSFET, a voltage has to be applied at gate so
as to exhaust the already existing carriers inside the channel. On the other
hand, enhancement type MOSFET is cut-off when gate and source are at same
voltage.
Taking the
example of NMOS, for a depletion MOS, with source and gate at same level, there
is still a channel available, hence, it conducts electric current. To bring it
to cut-off, a negative potential is needed to be applied at gate (considering
source at ‘X’ potential). Thus, with source at ‘X’ potential and gate at ‘X’
potential, drain attains the potential of source. Since, to cut-off the device,
gate has to be given a voltage less than ‘X’, so we can say “when Gate is 1 and
source is 1, then drain is 1”. On the
other hand, when source is 1 and gate is 0, drain attains ‘high impedance’. The
reverse is true for PMOS.
Similarly, with
the same logic, for an enhancement NMOS, “When Gate is 1 and source is 0, drain
attains 0 potential”; similarly, “When Gate is 0 and source is 0, drain is 0”.
The reverse is true for PMOS.
Source voltage
|
Gate voltage
|
Drain voltage for enhancement NMOS
|
Drain voltage for enhancement PMOS
|
Drain voltage for depletion NMOS
|
Drain voltage for depletion PMOS
|
0
|
0
|
Z
|
Z
|
0
|
0
|
0
|
1
|
0
|
Z
|
0
|
Z
|
1
|
0
|
Z
|
1
|
Z
|
1
|
1
|
1
|
Z
|
Z
|
1
|
1
|
Thus, we can say
that it is due to the inherent properties of NMOS and PMOS that that they
cannot be used to create negative level logic.