Static timing
analysis (STA) is an analysis method of computing the max/min delay values of a
complete circuit without actually simulating the full circuit. In STA, static
delays such as gate delay and net delays are considered in each path. These
delays are, then, compared against the required bounds on the delay values
and/or the relationship between the delays of different gates. In STA, the
circuit to be analyzed is broken down into timing paths consisting of gates,
registers and nets connecting these. Normally, timing paths start from and end
at registers or chip boundary. Based on origin and termination of data, timing
paths can be categorized into four categories:
1.)
Input to register paths: These paths start at
chip boundary from input ports and end at registers
2.)
Register to register paths: These paths start at
register output pin and terminate at register input pin
3.)
Register to output paths: These paths start at a
register and end at chip boundary output ports
4.)
Input to output paths: These paths start from
chip boundary at input port and end at chip boundary at output port
Timing path from
each start-point to end-point are constrained to have maximum and minimum
delays. For example, for register to register paths, each path can take maximum
of one clock cycle (minus input/output delay in case of input/output to
register paths). The minimum delay of a path is governed by hold timing
requirement of the endpoints. Thus, the maximum delay taken by a timing path
governs the maximum frequency of operation.
As stated
before, Static timing analysis does timing analysis without actually simulating
the circuit. The delays of cells are picked from respecting technology
libraries. The delays are available in libraries in tabulated form on the basis
of input transition and output load, which have been calculated based by
simulating the cells for a range of boundary conditions. Net delays are
calculated based upon R and C models.
One important
characteristic of static timing analysis that must be discussed is that static
timing analysis checks the static delay requirements of the circuit without
applying any vectors, hence, the delays calculated are the maximum and minimum
bounds of the delays that will occur in real application scenarios with vectors
applied. This enables the static timing analysis to be fast and inclusive of
all the boundary conditions. Dynamic timing analysis, on the contrary, applies
input vectors, so is very slow. It is necessary to certify the functionality of
the design. Thus, static timing analysis guarantees the timing of the design
whereas dynamic timing analysis guarantees functionality for real application
specific input vectors.
I hope you’ve found this post useful. Let me know what you think in the comments. I’d love to hear from you all.
