XOR/XNOR gate using 2:1 MUX

2-input XOR gate using a 2:1 multiplexer: As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select input. The function of a 2:1 multiplexer can be given as:

OUT = IN0 when SEL = 0 ELSE IN1

Also, a 2-input XOR gate produces a ‘1’ at the output if both the inputs have different value; and ‘0’ if the inputs are same. The truth table of an XOR gate is given as:

A
B
OUT
0
0
0
0
1
1
1
0
1
1
1
0
Truth table of XOR gate

In the truth table of XOR gate, if we fix a value, say B, then

OUT = A WHEN B = 0 ELSE A’


Both the above equations seem equivalent if we connect negative of IN0 to IN1 in a multiplexer. This is how a 2:1 multiplexer will implement an XOR gate. Figure 1 below shows the implement of a 2-input XOR gate using a 2:1 Multiplexer.

An XOR gate can be implemented from a mux simply by connecting the select to one of the inputs, and the inputs to A and Abar respectively.
Implementing a 2-input XOR gate using a 2:1 Multiplexer


I hope you’ve found this post useful. Let me know what you think in the comments. I’d love to hear from you all.


2-input XNOR gate using a 2:1 multiplexer: Similarly, the truth table of XNOR gate can be written as:

A
B
OUT
0
0
1
0
1
0
1
0
0
1
1
1
Truth table of XNOR gate

In the truth table, if we fix, say A, then

OUT = B WHEN A = 1, ELSE B’


Thus, XNOR gate is the complement of XOR gate. It can be implemented if we connect A to IN1 and Abar to IN0.

An XNOR gate can be implemented from a mux simply by connecting the select to one of the inputs, and the inputs to A and Abar respectively.
2-input XNOR gate using 2:1 multiplexer


Read also:

Latch using 2:1 MUX

As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select input. Also, a latch holds its previous value when its enable pin is in a particular state (‘0’ for positive level sensitive latch and ‘1’ for negative level sensitive latch).

So, to build a positive level sensitive latch from a multiplexer, short the output with IN0 pin of the multiplexer and connect data input to IN1 and Clock input to SEL pin of multiplexer. A negative level latch can also be built similarly. Figure 1 below shows the diagram representation for the same.

Build a latch using a multiplexer


Hope you’ve found this post useful. Let us know what you think in the comments.

Also read: