Latch using 2:1 MUX

As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select input. Also, a latch holds its previous value when its enable pin is in a particular state (‘0’ for positive level sensitive latch and ‘1’ for negative level sensitive latch).

So, to build a positive level sensitive latch from a multiplexer, short the output with IN0 pin of the multiplexer and connect data input to IN1 and Clock input to SEL pin of multiplexer. A negative level latch can also be built similarly. Figure 1 below shows the diagram representation for the same.

Build a latch using a multiplexer

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Also read:

• Implement 3 and 4 variable functions using a 8:1 mux
• Clock gating checks at a mux
• Multicycle paths - the architectural perspective
• What is logic built-in self test (LBIST)
• How propagation of 'X' happens through different logic gates