Metal ECO - the process

A metal-only ECO is carried out by changing only metal interconnects in the design. Metal-only ECOs are very common in today’s semiconductor industry as they save complete silicon re-spin. Sometimes there may be need to change the design for various reasons, and that too, a minor change. These changes may be due to some bug in the design or due to customer demand. A metal-only ECO enables the design to be re-fabricated only for a few layers. It is very cost-effective as for complete silicon re-spin, there may be a requirement of around 100 layer masks to be manufactured. Metal-only ECOs enable the older masks to be used for most of the layers. Only the layers with changes in them need to be manufactured again, which is usually 2 to 4 in case of metal-only ECOs.

The steps to carry out metal-only ECOs are explained below:

1.) A number of spare cells are sprinkled throughout the design before being taped-out so as to facilitate metal layer ECOs later on. The set of spare cells is chosen very carefully considering in mind the nature of design and the probability of metal ECO later on (it depends upon how mature the design building blocks are)

2.)  First, the changes to be made are evaluated if these can be carried out by changing only metal layers. For this purpose, spare cells in the vicinity of the ECO location need to be observed. If there is enough number of spare cells there, these can be used. On the other hand, if there is not enough number of spare cells to represent the logic change, the ECO cannot be carried out using only metal layers. It has to be, then, carried out using all the layers as more cells will need to be added. It will, then, result in re-spin of the design. 

3.) If there is enough number of spare cells available, the appropriate spare cells to represent the design change are selected in the vicinity of the logic to be changed. Interconnects are, then, modified so as to represent the modified circuit. 

4.) The resulting layout is checked for timing and DRC/LVS violations. If everything is fine, the design is sent to be fabricated. There, masks for the modified layers are manufactured using the older masks for layers not modified.

5.) If there is any violation related to timing or DRC/LVS, steps 2, 3 and 4 are repeated until the design is clean with respect to these.

Also read:

• Engineering Change Order (ECO)
• Routing - connecting the dots withing chip
• Setup time and hold time - static timing analysis
• Timing corners - dimensions in timing signoff
• Can a net have negative propagation delay

References –

·         http://www.cadence.com/Community/blogs/ii/archive/2010/11/23/user-interview-how-metal-only-ecos-save-full-silicon-respins.aspx

Spare Cells

We have discussed in our post titled 'Engineering Change Order' about the important to have a uniform distribution of spare cells in the design. Nowadays, there is a trend among the VLSI corporations to implement metal-only functional and timing ECOs due to their low-cost. Let us discuss about the spare cells in a bit more detail here.

Figure showing spare cells in the design

Spare cells are put onto the chip during implementation keeping into view the possibility of modifications that are planned to be carried out into the design without disturbing the layers of base. This is because carrying out design changes with minimal layer changes saves a lot of cost from fabrication point of view as each layer mask has a significant cost of its own. Let us start by defining what a spare cell is. A spare cell can be thought of as a redundant cell that is not used currently in the design. It may be in use later on, but currently, it is sitting without doing any job. A spare cell does not contribute to the functionality of the device. We can compare a spare cell with a spare wheel being carried in a motor car to be used in case one of the wheels gets punctured. In that case, the spare wheel will be replacing the main wheel. Similarly, a spare cell can be used to replace an existing cell if the situation demands (eg. to meet the timing). However, unlike spare wheels, spare cells may be added to the design even if they do not replace any existing cell according as the need arises.

Kinds of spare cells: There are many variants of spare cells in the design. Designs are full of spare inverters, buffers, nand, nor and specially designed configurable spare cells. However, based on the origin of spare cells, these can be divided into two broad categories:

• Those used deliberately as spare cells in the design: As discussed earlier, most of the designs today have spare cells sprinkled uniformly. These cells have inputs and outputs tied to either ‘0’ or ‘1’ so that they contribute minimum to static and dynamic power.
• Those converted into spare cells due to design changes: There may be a case that a cell that is being identified as a spare now was a main cell in the past. Due to some design changes, the cell might have been replaced by another cell. Also, some cells have floating outputs. These can be used as spare cells. We can also use the used buffers as spare cells if removing the buffer does not introduce any setup/hold violation in the design.

Advantages of using spare cells in the design: Introduction of spare cells into the design offers several advantages such as:

• Reusability: A design change can be carried out using metal layers only. So, the base layers can be re-used for fabrication of new chips.
• Cost reduction: Significant amount of money is saved both in terms of engineering and manufacture costs.
• Design flexibility: As there are spare cells, small changes can be taken into the design without much difficulty. Hence, the presence of spare cells provides flexibility to the design.
• Cycle time reduction: Nowadays, there is a trend to tape out base layers to the foundry for fabrication as masks are not prepared in parallel. In the meantime, the timing violations/design changes are being carried out in metal layers. Hence, there is cycle time reduction of one to two weeks.

Disadvantages of using spare cells: In addition to many advantages, usage of spare cells offers some disadvantages too. These are:

• Contribution to static power: Each spare cell has its static power dissipation. Hence, greater amount of spare cells contribute more to power. But, in general, this amount of power is insignificant in comparison to total power. Spare cells should be added keeping into consideration their contribution to power.
• Area: Spare cells occupy area on the chip. So, more spare cells mean more density of cells.

Thus, we have discussed about the spare cells here. Spare cells are used almost in every design in each device manufactured today. It is important to make an intelligent selection of spare cells to be sprinkled in the design. Many technical papers have been published stating its importance and on the structure of the spare cells that can be generalized to be used as any of the logic gate. In general, a collection of nand/nor/inverters/buffers is sprinkled more or less uniformly. The modules where more number of ECOs are expected, (like a new architecture being used for the first time) should be sprinkled with more spare cells. On the contrary, those having stable architectures are usually sprinkled with less number of spare cells as the probability of an ECO is very less in the vicinity of these modules/macros.

I hope you’ve found this post useful. Let me know what you think in the comments. I’d love to hear from you all.