How propagation of ‘X’ happens through different logic gates

‘X’ refers to a signal attaining a value that is ‘unknown’. It can be either ‘0’ or ‘1’. But, the exact value of the signal is not known. If a simulator is not able to decide whether a logic value should be logic ‘0’ or logic ‘1’, it will assign a value ‘X’ to the value. An example of ‘X’ source is a logic block that has not been initialized properly through reset. Having an ‘X’ value at a node can propagate to the logic lying in the fan-out, thereby increasing the uncertainty downstream the logic.

How ‘X’ propagates: An ‘X’ value at the input of a logic gate may or may not propagate to its output depending upon the states at other inputs of the logic gate. Given below is how different logic gates react to ‘X’ values:

1)  OR gate: An OR gate can absorb an ‘X’ if the other input has logic ‘1’. Otherwise, ‘X’ propagates through it. Please refer figure 1 for explanation:

Figure 1: X-propagation through OR gate

2) AND gate: An AND gate can absorb ‘X’ if the other input has logic ‘0’. Otherwise, ‘X’ propagates through it. Please refer figure 2 for explanation:

Figure 2: X-propagation through AND gate

3) Buffer/inverter: Since, buffers/inverters are single input gates, an ‘X’ at the input means ‘X’ at the output.

4) XOR gate: An ‘X’ at one of the inputs of XOR produces ‘X’ at the output no matter what the 

other input state is. Please refer truth table given in Figure 3 for explanation:

Figure 3: X-propagation through XOR gate

5) Complex gates: For complex gates, whether ‘X’ will propagate to the output depends upon the overall function of the ‘X’ input with respect to other gates. E.g. suppose a gate with function

Z = A + (B * C)

Then, if B input goes ‘X’, the output will go ‘X’ if A=0 and C=1.

Read also:

• Carry Look Ahead Adder
• MBIST (Memory Built-In Self Test)
• Controllability and observability - two DFT principles
• Digital counters
• Regions of operation of MOS transistors

Can a net have negative propagation delay?

As we discussed in ‘’Is it possible for a logic gate to have negative propagation delay”, a logic cell can have negative propagation delay. However, the only condition we mentioned was that the transition at the output pin should be improved drastically so that 50% level at output is reached before 50% level of input waveform.

In other words, the only condition for negative delay is to have improvement in slew. As we know, a net has only passive parasitic in the form of parasitic resistances and capacitances. Passive elements can only degrade the transition as they cannot provide energy (assuming no crosstalk); rather can only dissipate it. In other words, it is not possible for a net to have negative propagation delay.

However, we can have negative delay for a net, if there is crosstalk, as crosstalk can improve the transition on a net. In other words, in the presence of crosstalk, we can have 50% level at output reached before 50% level at input; hence, negative propagation delay of a net.

Also read:

• Bubble errors and bubble error correction
• Noise margins
• Can hold be frequency dependant
• Worst slew propagation
• Latchup in CMOS devices