Metal ECO - the process

A metal-only ECO is carried out by changing only metal interconnects in the design. Metal-only ECOs are very common in today’s semiconductor industry as they save complete silicon re-spin. Sometimes there may be need to change the design for various reasons, and that too, a minor change. These changes may be due to some bug in the design or due to customer demand. A metal-only ECO enables the design to be re-fabricated only for a few layers. It is very cost-effective as for complete silicon re-spin, there may be a requirement of around 100 layer masks to be manufactured. Metal-only ECOs enable the older masks to be used for most of the layers. Only the layers with changes in them need to be manufactured again, which is usually 2 to 4 in case of metal-only ECOs.

The steps to carry out metal-only ECOs are explained below:

1.) A number of spare cells are sprinkled throughout the design before being taped-out so as to facilitate metal layer ECOs later on. The set of spare cells is chosen very carefully considering in mind the nature of design and the probability of metal ECO later on (it depends upon how mature the design building blocks are)

2.)  First, the changes to be made are evaluated if these can be carried out by changing only metal layers. For this purpose, spare cells in the vicinity of the ECO location need to be observed. If there is enough number of spare cells there, these can be used. On the other hand, if there is not enough number of spare cells to represent the logic change, the ECO cannot be carried out using only metal layers. It has to be, then, carried out using all the layers as more cells will need to be added. It will, then, result in re-spin of the design. 

3.) If there is enough number of spare cells available, the appropriate spare cells to represent the design change are selected in the vicinity of the logic to be changed. Interconnects are, then, modified so as to represent the modified circuit. 

4.) The resulting layout is checked for timing and DRC/LVS violations. If everything is fine, the design is sent to be fabricated. There, masks for the modified layers are manufactured using the older masks for layers not modified.

5.) If there is any violation related to timing or DRC/LVS, steps 2, 3 and 4 are repeated until the design is clean with respect to these.

Also read:

• Engineering Change Order (ECO)
• Routing - connecting the dots withing chip
• Setup time and hold time - static timing analysis
• Timing corners - dimensions in timing signoff
• Can a net have negative propagation delay

References –

·         http://www.cadence.com/Community/blogs/ii/archive/2010/11/23/user-interview-how-metal-only-ecos-save-full-silicon-respins.aspx

Digital Counters

Digital Counters, as the name suggests, are digital circuits used for counting occurrence of any event. For any digital system like a computer, counters are most useful and versatile subsystem. A flip-flop can be used as a counter to count two states since Flip flop has two states either 0 or 1. Similarly, two flip-flops can be connected together to count 4 states (00, 01, 10, 11). Thus, with n flip-flops, we can make a counter that can count maximum 2ⁿ stages . Digital counters have following properties:

1)      Asynchronous or Synchronous – Asynchronous counters are one in which output of one flip-flop drives succeeding FF. Only first FF needs clock. All other Flops will be driven by its preceding FF. While in synchronous counters All FF are clocked by same external clock pulse.    

2)      Maximum number of counts – Also known as Modulus of counter. Modulus of counter is equal to total number of distinct stages through which counter progresses. For example:  A 4 Flip flop counter is often referred to as mod-16 counter i.e it can count 16 stages.

3)      Up or down counter – It dictates whether counter counts in upward or downward direction. For exp . 0 ->1->2->3->4->5->6->7 is up counter. 7->6->5->4->3->2->1->0 is down counter. The counter which can count in up or down direction depending upon some external signal(e.g.  if up(some external signal) is 1, count in upward direction else in downward) is called up-down counter.

4)      Free running or self stopping – if counter begins counting again after reaching its maximum stage,counter is called free running and if it stops after reaching maximum stage value it is called self stopping. Free running counters are also known as blind running counters.

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